公开(公告)号：US09196748B2

公开(公告)日：2015-11-24

申请号：US14146036

申请日：2014-01-02

Applicant: Renesas Electronics Corporation

Inventor： Kentaro Saito ,  Hiraku Chakihara

IPC: H01L29/66 ,  H01L29/788 ,  H01L29/423 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L27/11568 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/32133 ,  H01L27/1157 ,  H01L29/0642 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/792

Abstract: The performances of a semiconductor device are improved. The semiconductor device has a first control gate electrode and a second control gate electrode spaced along the gate length direction, a first cap insulation film formed over the first control gate electrode, and a second cap insulation film formed over the second control gate electrode. Further, the semiconductor device has a first memory gate electrode arranged on the side of the first control gate electrode opposite to the second control gate electrode, and a second memory gate electrode arranged on the side of the second control gate electrode opposite to the first control gate electrode. The end at the top surface of the first cap insulation film on the second control gate electrode side is situated closer to the first memory gate electrode side than the side surface of the first control gate electrode on the second control gate electrode side.

Abstract translation: 提高了半导体器件的性能。 半导体器件具有沿着栅极长度方向间隔开的第一控制栅电极和第二控制栅电极，形成在第一控制栅电极上的第一帽绝缘膜，以及形成在第二控制栅电极上的第二帽绝缘膜。 此外，半导体器件具有布置在与第二控制栅电极相对的第一控制栅极侧的第一存储栅极，以及布置在第二控制栅电极与第一控制栅相反的一侧的第二存储栅电极 栅电极。 第二控制栅电极侧的第一帽绝缘膜的顶面的端部比第二控制栅电极侧的第一控制栅电极的侧面更靠近第一存储栅电极侧。

公开(公告)号：US11456264B2

公开(公告)日：2022-09-27

申请号：US17148923

申请日：2021-01-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiaki Sato ,  Mitsunobu Wansawa ,  Akira Matsumoto ,  Yoshinori Deguchi ,  Kentaro Saito

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  G11C16/04 ,  H01L21/66

Abstract: In a method of manufacturing a semiconductor device according to one embodiment, after a semiconductor wafer including a non-volatile memory, a bonding pad and an insulating film comprised of an organic material is provided, a probe needle is contacted to a surface of the bonding pad located in a second region, and a data is written to the non-volatile memory. Here, the insulating film is formed by performing a first heat treatment to the organic material. Also, after a second heat treatment is performed to the semiconductor wafer, and the non-volatile memory to which the data is written is checked, a barrier layer and a first solder material are formed on the surface of the bonding pad located in a first region by using an electroplating method. Further, a bump electrode is formed in the first region by performing a third heat treatment to the first solder material.

公开(公告)号：US09831093B2

公开(公告)日：2017-11-28

申请号：US15236472

申请日：2016-08-14

Applicant: Renesas Electronics Corporation

Inventor： Kentaro Saito ,  Hideki Sugiyama ,  Hiraku Chakihara ,  Yoshiyuki Kawashima

IPC: H01L27/06 ,  H01L21/28 ,  H01L29/792 ,  H01L29/66 ,  H01L27/11573 ,  H01L49/02

CPC classification number: H01L21/28282 ,  H01L27/0629 ,  H01L27/11573 ,  H01L28/60 ,  H01L29/66833 ,  H01L29/792

Abstract: In a semiconductor device, a memory cell is formed of a control gate electrode and a memory gate electrode adjacent to each other, a gate insulating film formed below the control gate electrode and an insulating film formed below the memory gate electrode and having a charge accumulating part therein. Also, in this semiconductor device, a capacitive element is formed of a lower electrode, an upper electrode and a capacitive insulating film formed between the upper electrode and the lower electrode. A thickness of the lower electrode is smaller than a thickness of the control gate electrode.

公开(公告)号：US20150255420A1

公开(公告)日：2015-09-10

申请号：US14639062

申请日：2015-03-04

Applicant: Renesas Electronics Corporation

Inventor： Kentaro Saito

IPC: H01L23/00 ,  H01L23/29 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/10 ,  H01L21/74

CPC classification number: H01L24/49 ,  H01L21/743 ,  H01L21/78 ,  H01L23/10 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/562 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/02235 ,  H01L2224/03009 ,  H01L2224/0361 ,  H01L2224/03827 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05557 ,  H01L2224/05624 ,  H01L2224/06179 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/00013 ,  H01L2924/00

Abstract: In order to improve the reliability of a semiconductor device, dummy wiring includes: a first dummy part provided to be spaced apart from and to be parallel to, of a plurality of sides that form a pad, a first side nearest to a corner; and a second dummy part provided to be spaced apart from and to be parallel to, of the sides that form the pad, a second side nearest to an edge side of a semiconductor chip. That is, the dummy wiring is formed by: a first dummy part extending along the first side of the pad; and a second dummy part extending along the second side of the pad.

Abstract translation: 为了提高半导体器件的可靠性，虚拟布线包括：设置成与形成垫的多个边隔开并平行的第一伪零件，最靠近拐角的第一边; 以及设置成与形成所述焊盘的侧面间隔开并且平行于所述焊盘的侧面的第二虚设部件，最靠近半导体芯片的边缘侧的第二侧面。 也就是说，虚拟布线通过以下方式形成：第一虚拟部分，沿着焊盘的第一侧延伸; 以及沿着所述垫的第二侧延伸的第二虚拟部分。

公开(公告)号：US20140077310A1

公开(公告)日：2014-03-20

申请号：US14089959

申请日：2013-11-26

Applicant: Renesas Electronics Corporation

Inventor： Yasushi Ishii ,  Hiraku Chakihara ,  Kentaro Saito

IPC: H01L27/088 ,  H01L21/28

CPC classification number: H01L27/088 ,  H01L21/28008 ,  H01L21/82 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823864

Abstract: An improvement is achieved in the manufacturing yield of a semiconductor device including a plurality of field effect transistors having different characteristics over the same substrate. By combining anisotropic dry etching with isotropic wet etching or isotropic dry etching, three types of sidewalls having different sidewall lengths are formed. By reducing the number of anisotropic dry etching steps, in a third n-type MISFET region and a third p-type MISFET region where layout densities are high, it is possible to prevent a semiconductor substrate from being partially cut between n-type gate electrodes adjacent to each other, between the n-type gate electrode and a p-type gate electrode adjacent to each other, and the p-type gate electrodes adjacent to each other.

Abstract translation: 在包括在相同基板上具有不同特性的多个场效应晶体管的半导体器件的制造成品率方面的改进。 通过将各向异性干法蚀刻与各向同性湿蚀刻或各向同性干法蚀刻相结合，形成具有不同侧壁长度的三种类型的侧壁。 通过减少各向异性干蚀刻步骤的数量，在布置密度高的第三n型MISFET区域和第三p型MISFET区域中，可以防止半导体衬底在n型栅极之间被部分切割 彼此相邻的n型栅电极和彼此相邻的p型栅极之间，以及彼此相邻的p型栅电极。

公开(公告)号：US08617974B2

公开(公告)日：2013-12-31

申请号：US13662509

申请日：2012-10-28

Applicant: Renesas Electronics Corporation

Inventor： Yasushi Ishii ,  Hiraku Chakihara ,  Kentaro Saito

IPC: H01L21/3205

CPC classification number: H01L27/088 ,  H01L21/28008 ,  H01L21/82 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823864

Abstract: An improvement is achieved in the manufacturing yield of a semiconductor device including a plurality of field effect transistors having different characteristics over the same substrate. By combining anisotropic dry etching with isotropic wet etching or isotropic dry etching, three types of sidewalls having different sidewall lengths are formed. By reducing the number of anisotropic dry etching steps, in a third n-type MISFET region and a third p-type MISFET region where layout densities are high, it is possible to prevent a semiconductor substrate from being partially cut between n-type gate electrodes adjacent to each other, between the n-type gate electrode and a p-type gate electrode adjacent to each other, and the p-type gate electrodes adjacent to each other.

公开(公告)号：US10002768B2

公开(公告)日：2018-06-19

申请号：US15796621

申请日：2017-10-27

Applicant: Renesas Electronics Corporation

Inventor： Kentaro Saito ,  Hideki Sugiyama ,  Hiraku Chakihara ,  Yoshiyuki Kawashima

IPC: H01L21/28 ,  H01L49/02 ,  H01L27/11573 ,  H01L27/06 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L29/40117 ,  H01L27/0629 ,  H01L27/11573 ,  H01L28/60 ,  H01L29/66833 ,  H01L29/792

Abstract: In a semiconductor device, a memory cell is formed of a control gate electrode and a memory gate electrode adjacent to each other, a gate insulating film formed below the control gate electrode and an insulating film formed below the memory gate electrode and having a charge accumulating part therein. Also, in this semiconductor device, a capacitive element is formed of a lower electrode, an upper electrode and a capacitive insulating film formed between the upper electrode and the lower electrode. A thickness of the lower electrode is smaller than a thickness of the control gate electrode.

公开(公告)号：US09373630B2

公开(公告)日：2016-06-21

申请号：US14989999

申请日：2016-01-07

Applicant: Renesas Electronics Corporation

Inventor： Koichi Toba ,  Hiraku Chakihara ,  Yoshiyuki Kawashima ,  Kentaro Saito ,  Takashi Hashimoto

IPC: H01L21/8234 ,  H01L27/115 ,  H01L27/092

CPC classification number: H01L29/7847 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/3105 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/0922 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833

Abstract: To improve a semiconductor device having a nonvolatile memory. A first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

Abstract translation: 改善具有非易失性存储器的半导体器件。 形成第一MISFET，第二MISFET和存储单元，并在其上形成由氧化硅膜制成的阻挡膜。 然后，在阻挡膜上形成由氮化硅膜构成的应力施加膜，除去第二MISFET和存储单元上的应力施加膜。 此后，进行热处理以向第一MISFET施加应力。 因此，SMT不应用于每个元件，而是被选择性地应用。 这可以降低由于形成应力施加膜的氮化硅膜中的H（氢）导致的第二MISFET的劣化程度。 这也可以由于形成应力施加膜的氮化硅膜中的H（氢）而降低存储单元的特性的劣化程度。

公开(公告)号：US20160148897A1

公开(公告)日：2016-05-26

申请号：US15009473

申请日：2016-01-28

Applicant: Renesas Electronics Corporation

Inventor： Kentaro Saito

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/10

CPC classification number: H01L24/49 ,  H01L21/743 ,  H01L21/78 ,  H01L23/10 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/562 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/02235 ,  H01L2224/03009 ,  H01L2224/0361 ,  H01L2224/03827 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05557 ,  H01L2224/05624 ,  H01L2224/06179 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/00013 ,  H01L2924/00

Abstract: A semiconductor device includes a corner constituted by a first side and a second side being perpendicular to the first side; and a plurality of pads including a first pad, arranged along the second side and formed over a semiconductor substrate. The first pad is arranged nearer the corner than other pads of the plurality of pads. The first pad includes a third side, a fourth side being perpendicular to the third side, a fifth side being parallel to the third side and a sixth side being perpendicular to a fifth side. The third side and the fourth side are nearer to the corner than the fifth side and sixth side. A first dummy wiring is formed along the first side. A second dummy wiring is formed along the second side. The first dummy wiring and the second dummy wiring are formed integrally with each other.

Abstract translation: 半导体器件包括由第一侧和第二侧垂直于第一侧构成的拐角; 以及包括第一衬垫的多个焊盘，沿着第二侧布置并形成在半导体衬底上。 第一垫布置成比多个垫中的其它垫更靠近拐角。 第一垫包括第三侧，第四侧垂直于第三侧，第五侧平行于第三侧，第六侧垂直于第五侧。 第三面和第四面比第五面和第六面靠近角落。 沿着第一侧形成第一虚拟布线。 沿着第二侧形成第二虚拟布线。 第一虚拟布线和第二虚拟布线彼此一体地形成。

公开(公告)号：US09324725B2

公开(公告)日：2016-04-26

申请号：US14884273

申请日：2015-10-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kentaro Saito ,  Hiraku Chakihara

IPC: H01L29/792 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/51 ,  H01L29/49 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L27/11568 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/32133 ,  H01L27/1157 ,  H01L29/0642 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/792

Abstract: The performances of a semiconductor device are improved. The semiconductor device has a first control gate electrode and a second control gate electrode spaced along the gate length direction, a first cap insulation film formed over the first control gate electrode, and a second cap insulation film formed over the second control gate electrode. Further, the semiconductor device has a first memory gate electrode arranged on the side of the first control gate electrode opposite to the second control gate electrode, and a second memory gate electrode arranged on the side of the second control gate electrode opposite to the first control gate electrode. The end at the top surface of the first cap insulation film on the second control gate electrode side is situated closer to the first memory gate electrode side than the side surface of the first control gate electrode on the second control gate electrode side.