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公开(公告)号:US11054597B2
公开(公告)日:2021-07-06
申请号:US16382076
申请日:2019-04-11
Applicant: ROCKLEY PHOTONICS LIMITED
Inventor: Vivek Raghunathan , Vivek Raghuraman , Karlheinz Muth , David Arlo Nelson , Chia-Te Chou , Brett Sawyer , SeungJae Lee
Abstract: An electro-optical package. In some embodiments, the electro-optical package includes a first electro-optical chip coupled to an array of optical fibers, and a first physical medium dependent integrated circuit coupled to the first electro-optical chip.
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公开(公告)号:US10921538B2
公开(公告)日:2021-02-16
申请号:US16382076
申请日:2019-04-11
Applicant: ROCKLEY PHOTONICS LIMITED
Inventor: Vivek Raghunathan , Vivek Raghuraman , Karlheinz Muth , David Arlo Nelson , Chia-Te Chou , Brett Sawyer , SeungJae Lee
Abstract: An electro-optical package. In some embodiments, the electro-optical package includes a first electro-optical chip coupled to an array of optical fibers, and a first physical medium dependent integrated circuit coupled to the first electro-optical chip.
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公开(公告)号:US20190333905A1
公开(公告)日:2019-10-31
申请号:US16393763
申请日:2019-04-24
Applicant: ROCKLEY PHOTONICS LIMITED
Inventor: Vivek Raghunathan , Vivek Raghuraman , Karlheinz Muth
IPC: H01L25/18 , H01L31/02 , H01L23/498 , H01L23/00 , H01L25/00
Abstract: An electro-optical package. In some embodiments, the package includes an electronic integrated circuit module, a first electro-optical component, and a photonic integrated circuit. The first electro-optical component may be in a top surface of the photonic integrated circuit. The electronic integrated circuit module may have a top surface facing toward and overlapping both a portion of the first electro-optical component, and a portion of the photonic integrated circuit.
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公开(公告)号:US20190243164A1
公开(公告)日:2019-08-08
申请号:US16383309
申请日:2019-04-12
Applicant: ROCKLEY PHOTONICS LIMITED
Inventor: David Arlo Nelson , Vivek Raghuraman , David Erich Tetzlaff , Karlheinz Muth , Vivek Raghunathan
IPC: G02F1/01 , H03F3/24 , H03F1/32 , H03K17/687 , H03F3/217 , G02F1/17 , H04B10/588 , H04B10/50
CPC classification number: G02F1/0121 , G02F1/17 , H03F1/3241 , H03F3/217 , H03F3/245 , H03K17/687 , H03K19/20 , H04B10/505 , H04B10/588
Abstract: A system including an optical engine. In some embodiments, the system includes an integrated circuit in a first-level package, and the system includes the optical engine, in the first-level package, and the optical engine includes an electro-optical chip.
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公开(公告)号:US11333907B2
公开(公告)日:2022-05-17
申请号:US16383309
申请日:2019-04-12
Applicant: ROCKLEY PHOTONICS LIMITED
Inventor: David Arlo Nelson , Vivek Raghuraman , David Erich Tetzlaff , Karlheinz Muth , Vivek Raghunathan
IPC: G02F1/01 , H03F1/32 , H04B10/50 , H04B10/588 , H03F3/217 , H03F3/24 , H03K17/687 , H03K19/20
Abstract: A system including an optical engine. In some embodiments, the system includes an integrated circuit in a first-level package, and the system includes the optical engine, in the first-level package, and the optical engine includes an electro-optical chip.
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公开(公告)号:US11573387B2
公开(公告)日:2023-02-07
申请号:US16836815
申请日:2020-03-31
Applicant: ROCKLEY PHOTONICS LIMITED
Inventor: Brett Sawyer , Seungjae Lee , Chia-Te Chou , Vivek Raghunathan , Vivek Raghuraman , Karlheinz Muth , David Arlo Nelson
Abstract: An optical engine. In some embodiments, the optical engine includes an electronic interfacing component including: an upper surface having a plurality of conductors for forming a corresponding plurality of connections to a host board, a lower surface having a plurality of conductors for forming a corresponding plurality of connections to one or more optoelectronic elements, and a plurality of vias extending from the lower surface to the upper surface.
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公开(公告)号:US20200225430A1
公开(公告)日:2020-07-16
申请号:US16836815
申请日:2020-03-31
Applicant: ROCKLEY PHOTONICS LIMITED
Inventor: Brett Sawyer , SEUNGJAE LEE , Chia-Te Chou , Vivek Raghunathan , Vivek Raghuraman , Karlheinz Muth , David Arlo Nelson
Abstract: An optical engine. In some embodiments, the optical engine includes an electronic interfacing component including: an upper surface having a plurality of conductors for forming a corresponding plurality of connections to a host board, a lower surface having a plurality of conductors for forming a corresponding plurality of connections to one or more optoelectronic elements, and a plurality of vias extending from the lower surface to the upper surface.
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公开(公告)号:US20190317287A1
公开(公告)日:2019-10-17
申请号:US16382076
申请日:2019-04-11
Applicant: ROCKLEY PHOTONICS LIMITED
Inventor: Vivek Raghunathan , Vivek Raghuraman , Karlheinz Muth , David Arlo Nelson , Chia-Te Chou , Brett Sawyer , SeungJae Lee
Abstract: An electro-optical package. In some embodiments, the electro-optical package includes a first electro-optical chip coupled to an array of optical fibers, and a first physical medium dependent integrated circuit coupled to the first electro-optical chip.
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公开(公告)号:US12292605B2
公开(公告)日:2025-05-06
申请号:US17641418
申请日:2020-09-11
Applicant: ROCKLEY PHOTONICS LIMITED
Inventor: Seungjae Lee , Chia-Te Chou , Vivek Raghunathan , Brett Sawyer
Abstract: A siliconized heterogeneous optical engine. In some embodiments, the siliconized heterogeneous optical engine includes a photonic integrated circuit; an electro-optical chip, on a top surface of the photonic integrated circuit; an electronic integrated circuit, on the top surface of the photonic integrated circuit; an interposer, on the top surface of the photonic integrated circuit; a redistribution layer, on a top surface of the interposer, the redistribution layer including a plurality of conductive traces; and a plurality of protruding conductors, on the conductive traces of the redistribution layer. The electronic integrated circuit may be electrically connected to the electro-optical chip and to a conductive trace of the plurality of conductive traces of the redistribution layer.
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公开(公告)号:US11923327B2
公开(公告)日:2024-03-05
申请号:US17596252
申请日:2020-06-05
Applicant: ROCKLEY PHOTONICS LIMITED
Inventor: Michael Lee , John Paul Drake , Ying Luo , Vivek Raghunathan , Brett Sawyer
CPC classification number: H01L24/06 , H01L24/02 , H01L24/03 , H01L24/05 , H01L25/167 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L2224/02313 , H01L2224/02331 , H01L2224/0235 , H01L2224/02375 , H01L2224/02381 , H01L2224/0239 , H01L2224/03462 , H01L2224/03614 , H01L2224/03914 , H01L2224/0401 , H01L2224/05008 , H01L2224/05015 , H01L2224/05018 , H01L2224/05024 , H01L2224/05073 , H01L2224/05082 , H01L2224/05083 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171 , H01L2224/05172 , H01L2224/05181 , H01L2224/05184 , H01L2224/05548 , H01L2224/05555 , H01L2224/05558 , H01L2224/05611 , H01L2224/05644 , H01L2224/06051 , H01L2224/061 , H01L2224/06102 , H01L2224/06505 , H01L2224/13083 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204
Abstract: A silicon integrated circuit. In some embodiments, the silicon integrated circuit includes a first conductive trace, on a top surface of the silicon integrated circuit, a dielectric layer, on the first conductive trace, and a second conductive trace, on the dielectric layer, connected to the first conductive trace through a first via.
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