Semiconductor apparatus for reducing parasitic capacitance

    公开(公告)号:US11289571B2

    公开(公告)日:2022-03-29

    申请号:US16922109

    申请日:2020-07-07

    Applicant: ROHM CO., LTD.

    Inventor: Keishi Watanabe

    Abstract: The present invention provides a diode chip, including: a semiconductor chip, including a p-type first semiconductor layer and an n-type second semiconductor layer formed on the first semiconductor layer; a first pad separation trench, formed on the semiconductor chip in a manner of penetrating the second semiconductor layer till reaching the first semiconductor layer, and forming a first internal parasitic capacitance between the first semiconductor layer and the second semiconductor layer by separating a portion of the semiconductor chip from other regions; an inter-insulation layer, covering the second semiconductor layer; and a first electrode layer, being opposite to the region separated by the first pad separation trench with the inter-insulation layer interposed in between, and forming, between the first electrode layer and the semiconductor chip, a first external parasitic capacitance connected in series to the first internal parasitic capacitance.

    CHIP CAPACITOR AND MANUFACTURING METHOD THEREOF

    公开(公告)号:US20200152380A1

    公开(公告)日:2020-05-14

    申请号:US16677591

    申请日:2019-11-07

    Applicant: ROHM CO., LTD.

    Inventor: Keishi Watanabe

    Abstract: The present disclosure provides a chip capacitor, including: a first capacitor unit formed over a substrate and including a first lower electrode, first dielectric layer and first upper electrode; a second insulating layer over the first capacitor unit; a second conductive layer over the second insulating layer, and includes a first wiring portion and a second wiring portion, the first wiring portion being connected to the first lower electrode by a first contact via and connected to a first pad by a third contact via, the second wiring portion being connected to the first upper electrode by a second contact via and connected to a second pad by a fourth contact via; a first external electrode connected to the first wiring portion; and a second external electrode connected to the second wiring portion.

    Diode chip
    5.
    发明授权

    公开(公告)号:US12113064B2

    公开(公告)日:2024-10-08

    申请号:US17018486

    申请日:2020-09-11

    Applicant: ROHM CO., LTD.

    CPC classification number: H01L27/0814 H01L29/861 H01L29/866

    Abstract: The present disclosure provides a diode chip capable of attaining excellent electrical characteristics.
    The present disclosure provides a diode chip (1), including: a semiconductor chip (10) having a first main surface (11); a first pin junction portion (31) formed on a surface of the first main surface (11) with a first polarity direction; a first diode pair (37) (rectifier pair) including a first pn junction portion (35) separated from the first pin junction portion (31) and formed in the semiconductor chip (10) with the first polarity direction and a first reversed pin junction portion (38) connected to the first pn junction portion (35) in reversed direction and formed on the first main surface (11) with a second polarity direction; and a first junction separation trench (46) formed on the first main surface (11) in a manner of separating the first pin junction portion (31) and the first diode pair (37).

    Chip capacitor and manufacturing method thereof

    公开(公告)号:US11101071B2

    公开(公告)日:2021-08-24

    申请号:US16677591

    申请日:2019-11-07

    Applicant: ROHM CO., LTD.

    Inventor: Keishi Watanabe

    Abstract: The present disclosure provides a chip capacitor, including: a first capacitor unit formed over a substrate and including a first lower electrode, first dielectric layer and first upper electrode; a second insulating layer over the first capacitor unit; a second conductive layer over the second insulating layer, and includes a first wiring portion and a second wiring portion, the first wiring portion being connected to the first lower electrode by a first contact via and connected to a first pad by a third contact via, the second wiring portion being connected to the first upper electrode by a second contact via and connected to a second pad by a fourth contact via; a first external electrode connected to the first wiring portion; and a second external electrode connected to the second wiring portion.

    Chip capacitor having capacitor region directly below external electrode

    公开(公告)号:US10607779B2

    公开(公告)日:2020-03-31

    申请号:US15492109

    申请日:2017-04-20

    Applicant: ROHM CO., LTD.

    Abstract: A chip capacitor includes a substrate having a main surface, a first conductive film including a first connecting region and a first capacitor forming region and formed on the main surface of the substrate, a dielectric film covering the first capacitor forming region of the first conductive film, a second conductive film including a second connecting region facing to the first capacitor forming region of the first conductive film across the dielectric film, and a second capacitor forming region facing to the first capacitor forming region of the first conductive film across the dielectric film, a first external electrode electrically connected to the first connecting region of the first conductive film, and a second external electrode electrically connected to the second connecting region of the second conductive film.

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