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    Integral power and ground structure for multi-chip modules
    7.
    发明授权
    Integral power and ground structure for multi-chip modules 失效
    多芯片模块的集成电源和接地结构

    公开(公告)号：US5353195A

    公开(公告)日：1994-10-04

    申请号：US87433

    申请日：1993-07-09

    申请人： Raymond A. Fillion ,  Robert J. Wojnarowski

    发明人： Raymond A. Fillion ,  Robert J. Wojnarowski

    IPC分类号： H01L23/50 ,  H01L23/538 ,  H05K7/02

    CPC分类号： H01L24/82 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/24 ,  H01L2224/24225 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92144 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043

    摘要： A multi-chip module includes a substrate supporting a plurality of chips. A dielectric layer which overlies the chips and the substrate has a connection surface and a substrate surface with metallization planes having plane openings patterned on each surface and vias aligned with predetermined pads on the chips and predetermined portions of the metallization plane of the substrate surface. An adhesive layer is situated between the substrate and the substrate surface of the dielectric layer, and a pattern of electrical conductors extends through the vias to interconnect selected chips and selected portions of the metallization planes. In a related design, the dielectric layer may be a board having chip openings and conductive through-connections aligned with predetermined portions of the metallization plane of the substrate surface. The board can be thick enough that chip wells are not necessary for each chip, in which case, a base dielectric layer having vias aligned with chip pads, through-connections and the connection surface overlies the board and supports a pattern of electrical conductors which interconnect the chips and metallization planes.

    摘要翻译： 多芯片模块包括支撑多个芯片的基板。 覆盖芯片和衬底的电介质层具有连接表面和衬底表面，其中金属化平面具有在每个表面上图案化的平面开口，并且与衬底表面的芯片和金属化平面的预定部分上的预定焊盘对准的通孔。 粘合剂层位于基底和介电层的基底表面之间，并且电导体的图形延伸穿过通孔以互连选定的切屑和金属化平面的选定部分。 在相关设计中，电介质层可以是具有芯片开口和与衬底表面的金属化平面的预定部分对准的导电贯穿连接的板。 板可以足够厚，使得每个芯片不需要芯片阱，在这种情况下，具有与芯片焊盘，通孔连接对准的通孔的基底介电层，并且连接表面覆盖在板上并且支撑电连接的图案 芯片和金属化平面。

    Electronic apparatus with improved thermal expansion match
    9.
    发明授权
    Electronic apparatus with improved thermal expansion match 失效
    具有改善的热膨胀匹配的电子设备

    公开(公告)号：US5324987A

    公开(公告)日：1994-06-28

    申请号：US45753

    申请日：1993-04-14

    申请人： Charles D. Iacovangelo ,  Raymond A. Fillion ,  James F. Burgess

    发明人： Charles D. Iacovangelo ,  Raymond A. Fillion ,  James F. Burgess

    IPC分类号： H01L23/373 ,  H01L23/02 ,  H01L39/02

    CPC分类号： H01L23/3732 ,  H01L2924/0002

    摘要： Differences in thermal expansion properties between integrated circuit chips, especially of gallium arsenide, and the dielectric substrates (especially diamond and aluminum nitride) on which said chips are mounted are accommodated by interposing between the substrate and the chip a base having diamond pedestals in combination with a material of higher coefficient of thermal expansion than the substrate, typically a metal such as copper or tungsten. The base may be integral with a diamond substrate or may be a shim interposed between the substrate and the chip.

    摘要翻译： 集成电路芯片（特别是砷化镓）和安装有所述芯片的电介质基板（特别是金刚石和氮化铝）之间的热膨胀特性的差异通过将衬底和芯片之间插入具有金刚石基座的基座来结合 比基板高的热膨胀系数的材料，通常是诸如铜或钨的金属。 基底可以与金刚石基底成一体，或者可以是衬底和芯片之间的垫片。