公开(公告)号：US09589887B2

公开(公告)日：2017-03-07

申请号：US14863264

申请日：2015-09-23

Applicant: Renesas Electronics Corporation

Inventor： Shinpei Watanabe ,  Shinichi Uchida ,  Tadashi Maeda ,  Kazuo Henmi

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/495 ,  H01L23/528 ,  H01L25/065 ,  H04B5/00 ,  H01F38/14 ,  H01L23/48 ,  H01L23/00 ,  H01L25/16

CPC classification number: H01L23/645 ,  H01F17/0013 ,  H01F38/14 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/48 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/528 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/162 ,  H01L28/10 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2225/06527 ,  H01L2924/13055 ,  H01L2924/181 ,  H04B5/0031 ,  H04B5/0081 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/01029 ,  H01L2924/01014

Abstract: Dielectric breakdown is prevented between opposing two semiconductor chips, to improve the reliability of a semiconductor device. A first semiconductor chip has a wiring structure including a plurality of wiring layers, a first coil formed in the wiring structure, and an insulation film formed over the wiring structure. A second semiconductor chip has a wiring structure including a plurality of wiring layers, a second coil formed over the wiring structure, and an insulation film formed over the wiring structure. The first semiconductor chip and the second semiconductor chip are stacked via an insulation sheet with the insulation film of the first semiconductor chip and the insulation film of the second semiconductor chip facing each other. The first coil and the second coil are magnetically coupled with each other. Then, in each of the first and second semiconductor chips, wires and dummy wires are formed at the uppermost-layer wiring layer.

Abstract translation: 在相对的两个半导体芯片之间防止介电击穿，以提高半导体器件的可靠性。 第一半导体芯片具有包括多个布线层的布线结构，在布线结构中形成的第一线圈和形成在布线结构上的绝缘膜。 第二半导体芯片具有包括多个布线层的布线结构，形成在布线结构上的第二线圈和形成在布线结构上的绝缘膜。 第一半导体芯片和第二半导体芯片通过绝缘片与第一半导体芯片的绝缘膜和第二半导体芯片的绝缘膜彼此面对而堆叠。 第一线圈和第二线圈彼此磁耦合。 然后，在第一和第二半导体芯片的每一个中，在最上层布线层形成布线和虚拟布线。

公开(公告)号：US10115684B2

公开(公告)日：2018-10-30

申请号：US15424059

申请日：2017-02-03

Applicant: Renesas Electronics Corporation

Inventor： Shinpei Watanabe ,  Shinichi Uchida ,  Tadashi Maeda ,  Kazuo Henmi

IPC: H01L23/64 ,  H01F38/14 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L49/02

Abstract: A semiconductor device includes a first semiconductor chip including a first plurality of wiring layers, and a first coil, a first bonding pad, and first dummy wires formed in an uppermost layer of the first plurality of the wiring layers, and a second semiconductor chip including a second plurality of wiring layers, a second coil, a second bonding pad, and second dummy wires formed in an uppermost layer of the second plurality of the wiring layers. The first semiconductor chip and the second semiconductor chip face each other via an insulation sheet. The first coil and the second coil are magnetically coupled with each other.

公开(公告)号：US20170148751A1

公开(公告)日：2017-05-25

申请号：US15424059

申请日：2017-02-03

Applicant: Renesas Electronics Corporation

Inventor： Shinpei WATANABE ,  Shinichi Uchida ,  Tadashi Maeda ,  Kazuo Henmi

IPC: H01L23/64 ,  H01F38/14 ,  H01L23/495 ,  H01L23/31 ,  H01L49/02 ,  H01L23/00

CPC classification number: H01L23/645 ,  H01F17/0013 ,  H01F38/14 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/48 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/528 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/162 ,  H01L28/10 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2225/06527 ,  H01L2924/13055 ,  H01L2924/181 ,  H04B5/0031 ,  H04B5/0081 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/01029 ,  H01L2924/01014

Abstract: A semiconductor device includes a first semiconductor chip including a first plurality of wiring layers, and a first coil, a first bonding pad, and first dummy wires formed in an uppermost layer of the first plurality of the wiring layers, and a second semiconductor chip including a second plurality of wiring layers, a second coil, a second bonding pad, and second dummy wires formed in an uppermost layer of the second plurality of the wiring layers. The first semiconductor chip and the second semiconductor chip face each other via an insulation sheet. The first coil and the second coil are magnetically coupled with each other.

公开(公告)号：US09466591B2

公开(公告)日：2016-10-11

申请号：US14989661

申请日：2016-01-06

Applicant: Renesas Electronics Corporation

Inventor： Shinpei Watanabe ,  Shinichi Uchida ,  Tadashi Maeda ,  Shigeru Tanaka

IPC: H01L49/02 ,  H01L25/065 ,  H04B5/00 ,  H01L23/522 ,  H01L23/64 ,  H01L27/06 ,  H01L23/495 ,  H01L23/00 ,  H01L23/62 ,  H01L23/31 ,  H01L27/092

CPC classification number: H01L25/0657 ,  H01L23/3185 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/62 ,  H01L23/645 ,  H01L24/32 ,  H01L24/73 ,  H01L27/0617 ,  H01L27/0922 ,  H01L28/10 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2225/06531 ,  H01L2225/06562 ,  H01L2924/1206 ,  H01L2924/181 ,  H01L2924/19042 ,  H04B5/005 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device includes a first semiconductor chip that includes a first main surface, a first inductor formed on the first main surface, and a first external connection terminal formed on the first main surface; a second semiconductor chip that includes a second main surface, a second inductor formed on the second main surface, a second external connection terminal formed on the second main surface; and a first insulating film that is located between the first semiconductor chip and the second semiconductor chip, wherein the first semiconductor chip and the second semiconductor chip overlap each other such that the first main surface and the second main face each other, the semiconductor device includes a facing region in which the first semiconductor chip and the second semiconductor chip overlap each other when seen in a plan view.

Abstract translation: 半导体器件包括：第一半导体芯片，包括第一主表面，形成在第一主表面上的第一电感器和形成在第一主表面上的第一外部连接端子; 第二半导体芯片，包括第二主表面，形成在第二主表面上的第二电感器，形成在第二主表面上的第二外部连接端子; 以及位于所述第一半导体芯片和所述第二半导体芯片之间的第一绝缘膜，其中所述第一半导体芯片和所述第二半导体芯片彼此重叠，使得所述第一主表面和所述第二主面彼此相对，所述半导体器件包括 当在平面图中看到第一半导体芯片和第二半导体芯片彼此重叠时的面对区域。

公开(公告)号：US09252200B2

公开(公告)日：2016-02-02

申请号：US14522481

申请日：2014-10-23

Applicant: Renesas Electronics Corporation

Inventor： Shinpei Watanabe ,  Shinichi Uchida ,  Tadashi Maeda ,  Shigeru Tanaka

IPC: H01L49/02 ,  H04B5/00 ,  H01L23/522 ,  H01L23/64 ,  H01L27/06 ,  H01L23/495 ,  H01L23/00 ,  H01L23/62 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3185 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/62 ,  H01L23/645 ,  H01L24/32 ,  H01L24/73 ,  H01L27/0617 ,  H01L27/0922 ,  H01L28/10 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2225/06531 ,  H01L2225/06562 ,  H01L2924/1206 ,  H01L2924/181 ,  H01L2924/19042 ,  H04B5/005 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In a first semiconductor chip, a first multilayer interconnect layer is formed on a first substrate, and a first inductor is formed in the first multilayer interconnect layer. In a second semiconductor chip, a second multilayer interconnect layer is formed on a second substrate. A second inductor is formed in the second multilayer interconnect layer. The first semiconductor chip and the second semiconductor chip overlap each other in a direction in which the first multilayer interconnect layer and the second multilayer interconnect layer face each other. In addition, the first inductor and the second inductor overlap each other when seen in a plan view. At least one end of a first insulating film does not overlap the end of a facing region, in a Y direction.

Abstract translation: 在第一半导体芯片中，在第一基板上形成第一多层互连层，在第一多层互连层中形成第一电感器。 在第二半导体芯片中，在第二基板上形成第二多层互连层。 第二电感器形成在第二多层互连层中。 第一半导体芯片和第二半导体芯片在第一多层互连层和第二多层互连层彼此面对的方向上彼此重叠。 此外，当在平面图中看时，第一电感器和第二电感器彼此重叠。 第一绝缘膜的至少一端在Y方向上不与面对区域的端部重叠。

公开(公告)号：US20150130022A1

公开(公告)日：2015-05-14

申请号：US14522481

申请日：2014-10-23

Applicant: Renesas Electronics Corporation

Inventor： Shinpei Watanabe ,  Shinichi Uchida ,  Tadashi Maeda ,  Shigeru Tanaka

IPC: H01L49/02 ,  H01L27/01 ,  H04B5/00

CPC classification number: H01L25/0657 ,  H01L23/3185 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/62 ,  H01L23/645 ,  H01L24/32 ,  H01L24/73 ,  H01L27/0617 ,  H01L27/0922 ,  H01L28/10 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2225/06531 ,  H01L2225/06562 ,  H01L2924/1206 ,  H01L2924/181 ,  H01L2924/19042 ,  H04B5/005 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In a first semiconductor chip, a first multilayer interconnect layer is formed on a first substrate, and a first inductor is formed in the first multilayer interconnect layer. In a second semiconductor chip, a second multilayer interconnect layer is formed on a second substrate. A second inductor is formed in the second multilayer interconnect layer. The first semiconductor chip and the second semiconductor chip overlap each other in a direction in which the first multilayer interconnect layer and the second multilayer interconnect layer face each other. In addition, the first inductor and the second inductor overlap each other when seen in a plan view. At least one end of a first insulating film does not overlap the end of a facing region, in a Y direction.

Abstract translation: 在第一半导体芯片中，在第一基板上形成第一多层互连层，在第一多层互连层中形成第一电感器。 在第二半导体芯片中，在第二基板上形成第二多层互连层。 第二电感器形成在第二多层互连层中。 第一半导体芯片和第二半导体芯片在第一多层互连层和第二多层互连层彼此面对的方向上彼此重叠。 此外，当在平面图中看时，第一电感器和第二电感器彼此重叠。 第一绝缘膜的至少一端在Y方向上不与面对区域的端部重叠。