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公开(公告)号：US09589887B2
公开(公告)日：2017-03-07
申请号：US14863264
申请日：2015-09-23
Applicant: Renesas Electronics Corporation
Inventor： Shinpei Watanabe , Shinichi Uchida , Tadashi Maeda , Kazuo Henmi
IPC: H01L23/522 , H01L23/31 , H01L23/495 , H01L23/528 , H01L25/065 , H04B5/00 , H01F38/14 , H01L23/48 , H01L23/00 , H01L25/16
CPC classification number: H01L23/645 , H01F17/0013 , H01F38/14 , H01L23/3107 , H01L23/3114 , H01L23/48 , H01L23/49513 , H01L23/4952 , H01L23/49541 , H01L23/49575 , H01L23/5227 , H01L23/528 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L25/16 , H01L25/162 , H01L28/10 , H01L2224/02166 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/32145 , H01L2224/32245 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48245 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73215 , H01L2224/73265 , H01L2224/92147 , H01L2224/92247 , H01L2225/06527 , H01L2924/13055 , H01L2924/181 , H04B5/0031 , H04B5/0081 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2924/013 , H01L2924/01029 , H01L2924/01014
Abstract: Dielectric breakdown is prevented between opposing two semiconductor chips, to improve the reliability of a semiconductor device. A first semiconductor chip has a wiring structure including a plurality of wiring layers, a first coil formed in the wiring structure, and an insulation film formed over the wiring structure. A second semiconductor chip has a wiring structure including a plurality of wiring layers, a second coil formed over the wiring structure, and an insulation film formed over the wiring structure. The first semiconductor chip and the second semiconductor chip are stacked via an insulation sheet with the insulation film of the first semiconductor chip and the insulation film of the second semiconductor chip facing each other. The first coil and the second coil are magnetically coupled with each other. Then, in each of the first and second semiconductor chips, wires and dummy wires are formed at the uppermost-layer wiring layer.
Abstract translation: 在相对的两个半导体芯片之间防止介电击穿，以提高半导体器件的可靠性。 第一半导体芯片具有包括多个布线层的布线结构，在布线结构中形成的第一线圈和形成在布线结构上的绝缘膜。 第二半导体芯片具有包括多个布线层的布线结构，形成在布线结构上的第二线圈和形成在布线结构上的绝缘膜。 第一半导体芯片和第二半导体芯片通过绝缘片与第一半导体芯片的绝缘膜和第二半导体芯片的绝缘膜彼此面对而堆叠。 第一线圈和第二线圈彼此磁耦合。 然后，在第一和第二半导体芯片的每一个中，在最上层布线层形成布线和虚拟布线。
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公开(公告)号：US10746812B2
公开(公告)日：2020-08-18
申请号：US16534522
申请日：2019-08-07
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Kazuo Henmi , Ken Katano
Abstract: A semiconductor device includes a semiconductor chip having first, second and third pads, first and second external terminals to which a power supply potential or a reference potential is supplied, first and second wires connecting the first and second external terminals and the first and second pads, and a third wire connecting the second external terminal and the third pad. The semiconductor chip further includes a first internal wiring connected to the first and second pads, a second internal wiring connected to the third pad, and a detection circuit. The detection circuit includes: a current source for passing a current through the first and second internal wirings; first and second resistive elements connected between the current source and the first and second internal wirings; and an amplifier circuit for amplifying a relative potential difference generated between the first and second resistive elements and outputting a detection signal.
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公开(公告)号：US10115684B2
公开(公告)日：2018-10-30
申请号：US15424059
申请日：2017-02-03
Applicant: Renesas Electronics Corporation
Inventor： Shinpei Watanabe , Shinichi Uchida , Tadashi Maeda , Kazuo Henmi
Abstract: A semiconductor device includes a first semiconductor chip including a first plurality of wiring layers, and a first coil, a first bonding pad, and first dummy wires formed in an uppermost layer of the first plurality of the wiring layers, and a second semiconductor chip including a second plurality of wiring layers, a second coil, a second bonding pad, and second dummy wires formed in an uppermost layer of the second plurality of the wiring layers. The first semiconductor chip and the second semiconductor chip face each other via an insulation sheet. The first coil and the second coil are magnetically coupled with each other.
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公开(公告)号：US20170148751A1
公开(公告)日：2017-05-25
申请号：US15424059
申请日：2017-02-03
Applicant: Renesas Electronics Corporation
Inventor： Shinpei WATANABE , Shinichi Uchida , Tadashi Maeda , Kazuo Henmi
CPC classification number: H01L23/645 , H01F17/0013 , H01F38/14 , H01L23/3107 , H01L23/3114 , H01L23/48 , H01L23/49513 , H01L23/4952 , H01L23/49541 , H01L23/49575 , H01L23/5227 , H01L23/528 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L25/16 , H01L25/162 , H01L28/10 , H01L2224/02166 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/32145 , H01L2224/32245 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48245 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73215 , H01L2224/73265 , H01L2224/92147 , H01L2224/92247 , H01L2225/06527 , H01L2924/13055 , H01L2924/181 , H04B5/0031 , H04B5/0081 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2924/013 , H01L2924/01029 , H01L2924/01014
Abstract: A semiconductor device includes a first semiconductor chip including a first plurality of wiring layers, and a first coil, a first bonding pad, and first dummy wires formed in an uppermost layer of the first plurality of the wiring layers, and a second semiconductor chip including a second plurality of wiring layers, a second coil, a second bonding pad, and second dummy wires formed in an uppermost layer of the second plurality of the wiring layers. The first semiconductor chip and the second semiconductor chip face each other via an insulation sheet. The first coil and the second coil are magnetically coupled with each other.
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