公开(公告)号：US20250105834A1

公开(公告)日：2025-03-27

申请号：US18885982

申请日：2024-09-16

Applicant: ROHM CO., LTD.

Inventor： Makoto SADA ,  Katsuaki YAMADA ,  Shuntaro TAKAHASHI ,  Toru TAKUMA ,  Naoki TAKAHASHI

IPC: H03K17/082

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes: a semiconductor substrate; a well, formed in the semiconductor substrate; an output terminal, electrically connected to the semiconductor substrate; a ground terminal, configured to receive a ground voltage; a detection signal generating circuit, configured to generate a negative current detection signal when an output voltage present at the output terminal is detected to be less than the ground voltage; and a control circuit, configured to apply the ground voltage or the output voltage to the well in response to the negative current detection signal. The detection signal generating circuit includes: a comparator, configured to generate the negative current detection signal by comparing an output detection voltage with the ground voltage or the threshold voltage; a bias circuit, configured to switch between applying the output voltage or a bias voltage as the output detection voltage; and a clamp circuit.

公开(公告)号：US20240007103A1

公开(公告)日：2024-01-04

申请号：US18468089

申请日：2023-09-15

Applicant: ROHM CO., LTD.

Inventor： Katsuaki YAMADA ,  Shuntaro TAKAHASHI ,  Muga IMAMURA

IPC: H03K17/687

CPC classification number: H03K17/687

Abstract: A switching device includes: an N-type semiconductor substrate; a power MISFET having the N-type semiconductor substrate as its drain; an input electrode receiving an input signal; a control circuit generating a gate control signal for the power MISFET according to the input signal; and a negative current prevention circuit provided between the input electrode and the control circuit. The negative current prevention circuit includes: a P-channel MISFET connected, with its drain toward the input electrode and its source and back gate toward the control circuit, between the input electrode and the control circuit, with its gate fed with a fixed potential, with the potential at its back gate separated from the potential of the N-type semiconductor substrate; and a diode connected, with its anode toward the input electrode and its cathode toward the control circuit, between the input electrode and the control circuit.

公开(公告)号：US20200212664A1

公开(公告)日：2020-07-02

申请号：US16726461

申请日：2019-12-24

Applicant: Rohm Co., Ltd.

Inventor： Toru TAKUMA ,  Shuntaro TAKAHASHI

IPC: H02H1/00 ,  B60R16/02 ,  H02H3/087 ,  H03K17/0812 ,  H03K17/14 ,  H03K19/003 ,  H03K17/687

Abstract: A switching device has, for example, a first terminal configured to be connected to an application node for a first voltage, a second terminal configured to be connected to the first end of a load, a third terminal configured to be connected to the second end of the load and to an application node for a second voltage, a switching element configured to be connected between the first and second terminals, a first active clamper configured to limit the output voltage at the second terminal with reference to the first voltage in a first state, and a second active clamper configured to limit the output voltage with reference to the second voltage in a second state different from the first state.

公开(公告)号：US20240097677A1

公开(公告)日：2024-03-21

申请号：US18463610

申请日：2023-09-08

Applicant: ROHM CO., LTD.

Inventor： Naoki TAKAHASHI ,  Shuntaro TAKAHASHI

IPC: H03K17/687 ,  B60R16/03

CPC classification number: H03K17/687 ,  B60R16/03

Abstract: A switching device, for example, includes a P-type semiconductor substrate configured to be fed with a ground voltage, a switching element connected between an application terminal for a supply voltage and an application terminal for an output voltage, a driver configured to turn on and off the switching element, and an active clamp circuit configured to control the switching element so as to keep the output voltage at an off transition of the switching element equal to or higher than a lower limit voltage lower than the ground voltage by an active clamp voltage.

公开(公告)号：US20230216289A1

公开(公告)日：2023-07-06

申请号：US18181064

申请日：2023-03-09

Applicant: Rohm Co. Ltd.

Inventor： Toru TAKUMA ,  Naoki TAKAHASHI ,  Shuntaro TAKAHASHI

IPC: H02H1/00 ,  H02H3/093 ,  B60R16/02 ,  H02H3/087 ,  H02H7/20 ,  B60R16/03

CPC classification number: H02H1/0007 ,  H02H3/093 ,  B60R16/02 ,  H02H3/087 ,  H02H7/20 ,  B60R16/03 ,  H02H7/205

Abstract: In order both to accommodate instantaneous current as well as overcurrent protection in accordance with the load, an overcurrent protection circuit has: a threshold value generation unit that, in accordance with a threshold value control signal, switches between setting an overcurrent detection threshold value to a first set value (∝ Iref) and a second set value (∝ Iset) lower than the first set value; an overcurrent detection unit that compares a sense signal in accordance with the current being monitored and the overcurrent detection value and generates an overcurrent protection signal; a reference value generation unit that generates a reference value (∝ Iset) in accordance with the seconds set value; a comparison unit that compares the sense signal and the reference value, and generates a comparison signal; and a threshold value control unit that monitors the comparison signal, and generates a threshold value control signal.

公开(公告)号：US20240421203A1

公开(公告)日：2024-12-19

申请号：US18820307

申请日：2024-08-30

Applicant: ROHM CO., LTD.

Inventor： Shojiro KATO ,  Keita OKAMOTO ,  Shuntaro TAKAHASHI

IPC: H01L29/417 ,  H01L23/538 ,  H01L27/02 ,  H01L27/088

Abstract: A semiconductor device includes an insulated gate type first transistor that is formed at a semiconductor chip, an insulated gate type second transistor that is formed at the semiconductor chip, and a control wiring that transmits a control signal controlling the first transistor and the second transistor to reach an ON state during a normal operation and controlling the first transistor to reach an OFF state and the second transistor to reach an ON state during an active clamp operation.

公开(公告)号：US20240087996A1

公开(公告)日：2024-03-14

申请号：US18510204

申请日：2023-11-15

Applicant: ROHM CO., LTD.

Inventor： Kazuki OKUYAMA ,  Shuntaro TAKAHASHI ,  Motoharu HAGA ,  Shingo YOSHIDA ,  Kazuhisa KUMAGAI ,  Hajime OKUDA

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L21/765 ,  H01L23/00 ,  H01L23/31 ,  H01L23/34 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/49562 ,  H01L21/4825 ,  H01L21/565 ,  H01L21/765 ,  H01L23/3114 ,  H01L23/34 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49582 ,  H01L24/48 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2224/48245 ,  H01L2224/48472 ,  H01L2924/13091

Abstract: A semiconductor device includes a semiconductor element and a first connection member. The semiconductor element includes a substrate and an electrode pad. The substrate includes a transistor formation region, in which a transistor is formed and which is shaped to be non-quadrangular. The electrode pad is located on the transistor formation region. The first connection member is connected to the electrode pad at one location. The electrode pad is arranged to cover a center of gravity of the transistor formation region in a plan view of the electrode pad. In the plan view, a connection region in which the first connection member is connected to the electrode pad includes a center of gravity position of the transistor formation region.

公开(公告)号：US20250069997A1

公开(公告)日：2025-02-27

申请号：US18945218

申请日：2024-11-12

Applicant: ROHM CO., LTD.

Inventor： Kazuki OKUYAMA ,  Shuntaro TAKAHASHI ,  Motoharu HAGA ,  Shingo YOSHIDA ,  Kazuhisa KUMAGAI ,  Hajime OKUDA

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L21/765 ,  H01L23/00 ,  H01L23/31 ,  H01L23/34 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor element and a first connection member. The semiconductor element includes a substrate and an electrode pad. The substrate includes a transistor formation region, in which a transistor is formed and which is shaped to be non-quadrangular. The electrode pad is located on the transistor formation region. The first connection member is connected to the electrode pad at one location. The electrode pad is arranged to cover a center of gravity of the transistor formation region in a plan view of the electrode pad. In the plan view, a connection region in which the first connection member is connected to the electrode pad includes a center of gravity position of the transistor formation region.

公开(公告)号：US20250055275A1

公开(公告)日：2025-02-13

申请号：US18792110

申请日：2024-08-01

Applicant: ROHM CO., LTD.

Inventor： Katsuaki YAMADA ,  Toru TAKUMA ,  Shuntaro TAKAHASHI

IPC: H02H9/02

Abstract: An overcurrent protection circuit that limits a current to be monitored based on a current limit signal includes: a first transistor and a second transistor configured to form an amplifier input stage that receives input of a detection signal according to the current to be monitored; a third transistor configured to generate a current output signal according to a difference between the detection signal and a reference signal, and configured to form an amplifier output stage that inputs the current output signal as a negative feedback to the amplifier input stage; and a current mirror circuit configured to generate the current limit signal by replicating a signal based on the current output signal.

公开(公告)号：US20240088886A1

公开(公告)日：2024-03-14

申请号：US18263404

申请日：2021-11-29

Applicant: Rohm Co., Ltd.

Inventor： Makoto SADA ,  Toru TAKUMA ,  Shuntaro TAKAHASHI

IPC: H03K17/0814 ,  H01L27/06 ,  H01L29/06 ,  H01L29/78

CPC classification number: H03K17/08142 ,  H01L27/0629 ,  H01L29/0696 ,  H01L29/7808 ,  H01L29/7813

Abstract: A semiconductor device 1 includes: a split-gate transistor 9 connected between a drain electrode 11 (output electrode OUT) and a ground electrode and having a plurality of individually controllable channel regions; an active clamp circuit 26 configured to limit the output voltage VOUT appearing at the output electrode 11 to a clamp voltage or below; and a gate control circuit 25 configured to raise the ON resistance of the split-gate transistor 9 gently (or stepwise) after the split-gate transistor is switched from the ON state to the OFF state before the active clamp circuit 26 limits the output voltage VOUT.