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    Wiring board providing impedance matching
    5.
    发明授权
    Wiring board providing impedance matching 有权
    接线板提供阻抗匹配

    公开(公告)号：US07339260B2

    公开(公告)日：2008-03-04

    申请号：US10927134

    申请日：2004-08-27

    申请人： Yasuhiro Sugimoto ,  Kazunaga Higo ,  Kazuhiro Suzuki

    发明人： Yasuhiro Sugimoto ,  Kazunaga Higo ,  Kazuhiro Suzuki

    IPC分类号： H01L23/12 ,  H01L23/02 ,  H05K3/46 ,  H05K1/02 ,  H01H29/40

    CPC分类号： H01L23/66 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0222 ,  H05K1/0251 ,  H05K1/113 ,  H05K3/4602 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09618 ,  H05K2201/09627 ,  H05K2201/0969 ,  H05K2201/09718 ,  H05K2201/09809

    摘要： A wiring board comprising: a plate core having a first main surface and a second main surface; conductor layers including a conductor line; dielectric layers laminated alternately with said conductor layers on at least one of said first and second main surfaces; via conductors as defined herein; a signal through-hole as defined herein; a signal through-hole conductor as defined herein; a first path end pad as defined herein; a second path end pad as defined herein; a shield through-hole as defined herein; and a shield through-hole conductor as defined herein; wherein: a signal transmission path is formed as defined herein; at least one of said conductor layers is disposed on each of said first and second main surface sides; said surface conductor on said first main surface side and said conductor line form a strip line, a microstrip line, or a coplanar waveguide with constant characteristic impedance Z0; an inner surface of said shield through-hole is covered with said shield through-hole conductor; and an interaxis distance between said signal through-hole conductor and said shield through-hole conductor is adjusted as defined herein.

    摘要翻译： 一种布线板，包括：板芯，具有第一主表面和第二主表面; 包括导体线的导体层; 电介质层与所述导体层交替地层叠在所述第一和第二主表面中的至少一个上; 通孔导体; 如本文所定义的信号通孔; 如本文所定义的信号通孔导体; 如本文所定义的第一路径端垫; 如本文所定义的第二路径端垫; 如本文所定义的屏蔽通孔; 和如本文所定义的屏蔽通孔导体; 其中：如本文所定义的形成信号传输路径; 所述导体层中的至少一个设置在所述第一和第二主表面侧的每一个上; 所述第一主表面侧的所述表面导体和所述导体线形成具有恒定特性阻抗Z 0的带状线，微带线或共面波导; 所述屏蔽通孔的内表面被所述屏蔽通孔导体覆盖; 并且如本文所定义的那样调整所述信号通孔导体和所述屏蔽通孔导体之间的间隔距离。

    Wiring board
    6.
    发明申请
    Wiring board 有权
    接线板

    公开(公告)号：US20060043572A1

    公开(公告)日：2006-03-02

    申请号：US10927134

    申请日：2004-08-27

    申请人： Yasuhiro Sugimoto ,  Kazunaga Higo ,  Kazuhiro Suzuki

    发明人： Yasuhiro Sugimoto ,  Kazunaga Higo ,  Kazuhiro Suzuki

    IPC分类号： H01L29/40

    CPC分类号： H01L23/66 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0222 ,  H05K1/0251 ,  H05K1/113 ,  H05K3/4602 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09618 ,  H05K2201/09627 ,  H05K2201/0969 ,  H05K2201/09718 ,  H05K2201/09809

    摘要： A wiring board comprising: a plate core having a first main surface and a second main surface; conductor layers including a conductor line; dielectric layers laminated alternately with said conductor layers on at least one of said first and second main surfaces; via conductors as defined herein; a signal through-hole as defined herein; a signal through-hole conductor as defined herein; a first path end pad as defined herein; a second path end pad as defined herein; a shield through-hole as defined herein; and a shield through-hole conductor as defined herein; wherein: a signal transmission path is formed as defined herein; at least one of said conductor layers is disposed on each of said first and second main surface sides; said surface conductor on said first main surface side and said conductor line form a strip line, a microstrip line, or a coplanar waveguide with constant characteristic impedance Z0; an inner surface of said shield through-hole is covered with said shield through-hole conductor; and an interaxis distance between said signal through-hole conductor and said shield through-hole conductor is adjusted as defined herein.

    摘要翻译： 一种布线板，包括：板芯，具有第一主表面和第二主表面; 包括导体线的导体层; 电介质层与所述导体层交替地层叠在所述第一和第二主表面中的至少一个上; 通孔导体; 如本文所定义的信号通孔; 如本文所定义的信号通孔导体; 如本文所定义的第一路径端垫; 如本文所定义的第二路径端垫; 如本文所定义的屏蔽通孔; 和如本文所定义的屏蔽通孔导体; 其中：如本文所定义的形成信号传输路径; 所述导体层中的至少一个设置在所述第一和第二主表面侧的每一个上; 所述第一主表面侧的所述表面导体和所述导体线形成具有恒定特性阻抗Z0的带状线，微带线或共面波导; 所述屏蔽通孔的内表面被所述屏蔽通孔导体覆盖; 并且如本文所定义的那样调节所述信号通孔导体和所述屏蔽通孔导体之间的间隔距离。

    Ceramic capacitor
    7.
    发明授权
    Ceramic capacitor 有权
    陶瓷电容器

    公开(公告)号：US07889509B2

    公开(公告)日：2011-02-15

    申请号：US11513039

    申请日：2006-08-31

    申请人： Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Yasuhiro Sugimoto

    发明人： Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Yasuhiro Sugimoto

    IPC分类号： H05K7/00

    CPC分类号： H05K1/185 ,  H01G2/06 ,  H01G4/385 ,  H01L23/49816 ,  H01L23/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/3025 ,  H05K1/0231 ,  H05K3/4602 ,  H05K2201/10045 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/05599

    摘要： A circuit board (10, 10″, 10′″) comprising: a board core (11) having a main core surface (12) and a rear core surface (13); a ceramic capacitor (101, 101′, 101″, 101′″, 101″″, 101″″′, 101″″″) having a main capacitor surface (102) and a rear capacitor surface (103), having a structure in which a first inner electrode layer (141) and a second inner electrode layer (142) are alternately stacked with a ceramic dielectric layer (105) interposed therebetween, and having a plurality of capacitor function units (107, 108) being electrically independent from each other, the ceramic capacitor (101, 101′, 101″, 101′″, 101″″, 101″″′, 101″″″) being buried in the board core (11) in a state where the main core surface (12) and the main capacitor surface (102) are directed in a same direction; and a buildup layer (31) having a structure in which an interlayer insulating layer (33, 35) and a conductor layer (42) are alternately stacked on the main core surface (12) and the main capacitor surface (102) and having a semiconductor integrated circuit device mounting region (23, 51, 52) for mounting a semiconductor integrated circuit device (21, 53, 54) having a plurality of processor cores (24, 25) on a surface (39) of the buildup layer (31), wherein the plurality of capacitor function units (107, 108) are capable of being electrically connected to the plurality of processor cores (24, 25), respectively.

    摘要翻译： 一种电路板（10,10“，10”），包括：具有主芯表面（12）和后芯表面（13）的板芯（11）; 具有主电容器表面（102）和后电容器表面（103）的陶瓷电容器（101,101'，101“，101”，101“”，101“”，101“”“）， 其中第一内部电极层（141）和第二内部电极层（142）交替层叠有介于其间的陶瓷介电层（105），并且具有多个电容器功能单元（107,108），其电独立于 相互之间的陶瓷电容器（101,101'，101“，101”，101“，101”，101“”101“”）被埋在板芯11中， （12）和主电容器表面（102）指向相同的方向; 以及具有层间绝缘层（33,35）和导体层（42）在主芯面（12）和主电容器表面（102）上交替层叠的结构的积层（31），具有 半导体集成电路器件安装区域（23,51,52），用于安装具有多个处理器核心（24,25）的半导体集成电路器件（21,53,54），所述多个处理器核心（24,25）在所述生成层（31）的表面（39）上 ），其中所述多个电容器功能单元（107,108）能够分别电连接到所述多个处理器核（24,25）。

    Constant voltage circuit
    9.
    发明授权
    Constant voltage circuit 失效
    恒压电路

    公开(公告)号：US5278491A

    公开(公告)日：1994-01-11

    申请号：US865663

    申请日：1992-04-07

    申请人： Shouzou Nitta ,  Yasuhiro Sugimoto

    发明人： Shouzou Nitta ,  Yasuhiro Sugimoto

    IPC分类号： G05F3/30 ,  G05F3/26

    CPC分类号： G05F3/30

    摘要： This invention discloses a constant voltage circuit including a bandgap circuit connected between a ground voltage and a source voltage, a transistor, the collector of which is connected to the collector of a negative feedback transistor for supplying a voltage of a base-emitter path to the other terminal of a resistor having one terminal connected to an output terminal of the bandgap circuit, and the base of which is connected to a voltage source free from variations in source voltage, and a resistor connected between the emitter of the transistor and the source voltage.

    摘要翻译： 本发明公开了一种包括连接在接地电压和源电压之间的带隙电路的恒压电路，晶体管，其集电极连接到负反馈晶体管的集电极，用于将基极 - 发射极路径的电压提供给 电阻器的另一个端子，其一个端子连接到带隙电路的输出端子，并且其基极连接到没有源极电压变化的电压源，以及连接在晶体管的发射极和源极电压之间的电阻器 。

    Attenuator circuit
    10.
    发明授权
    Attenuator circuit 失效
    衰减器电路

    公开(公告)号：US4912394A

    公开(公告)日：1990-03-27

    申请号：US355610

    申请日：1989-05-23

    申请人： Yasuhiro Sugimoto ,  Hiromi Mafune

    发明人： Yasuhiro Sugimoto ,  Hiromi Mafune

    IPC分类号： H03H7/24

    CPC分类号： H03H7/24

    摘要： An attenuator circuit is provided which comprises an input node, a first resistor connected at one terminal to a reference potential, a second resistor connected to the other terminal of the first resistor, a first output node which is a connection node of the first resistor and the second resistor, a third resistor connected in parallel with the series circuit of the first and second resistors and being of such a type that a resultant resistive value of the first, second and third resistors is equal to a resistive value of the first resistor, a fourth resistor connected at one terminal to a connection node of the second and third resistors and having a resistive value substantially equal to that of the second resistor, and at least one combination resistor of a ladder configuration connected between the other terminal of the fourth resistor and the input node and having a third output node as a junction of its series circuit portion.

    摘要翻译： 提供了一种衰减器电路，其包括输入节点，在一个端子处连接到参考电位的第一电阻器，连接到第一电阻器的另一端子的第二电阻器，作为第一电阻器的连接节点的第一输出节点和 第二电阻器，与第一和第二电阻器的串联电路并联连接的第三电阻器，并且是第一，第二和第三电阻器的合成电阻值等于第一电阻器的电阻值的类型， 在一个端子处连接到第二和第三电阻器的连接节点并且具有基本上等于第二电阻器的电阻值的电阻值的第四电阻器，以及连接在第四电阻器的另一个端子之间的梯形配置的至少一个组合电阻器 和输入节点，并具有作为其串联电路部分的结点的第三输出节点。