公开(公告)号：US06379987B1

公开(公告)日：2002-04-30

申请号：US09790346

申请日：2001-02-21

申请人： Ronald Dekker ,  Wilhelmus Mathias Clemens Dolmans ,  Lukas Leyten ,  Henricus Godefridus Rafael Maas

发明人： Ronald Dekker ,  Wilhelmus Mathias Clemens Dolmans ,  Lukas Leyten ,  Henricus Godefridus Rafael Maas

IPC分类号： H01L2100

CPC分类号： H03H3/02 ,  H03H9/0542

摘要： A method of manufacturing a hybrid integrated circuit comprising a semiconductor element (1) and a piezoelectric filter (2), which are situated next to each other and connected to a carrier substrate (3). The semiconductor element comprises semiconductor regions (5, 6) which are formed in a silicon layer (13, 28); the piezoelectric filter comprises an acoustic resonator (8, 9, 10) which is situated on an acoustic reflector layer (7), which acoustic resonator comprises a layer of piezoelectric material (8), a first electrode (9) situated between the layer of piezoelectric material and the acoustic reflector layer, and a second electrode (10) which is situated on the opposite side of the piezoelectric layer and faces the first electrode. In the method, the semiconductor element is formed on the first side (11) of a silicon wafer (12, 25). On the same side of this wafer, also the layer of piezoelectric material and the first electrode are formed, after which the surface is covered with the acoustic reflector layer. Subsequently, an adhesive layer (22) is used to attach the structure thus formed with the acoustic reflector layer to the carrier substrate. Finally, at the location of the filter, silicon is removed from the second side of the wafer, and the comparatively thick acoustic reflector need not be patterned so that underlying features cannot be damaged during etching said reflector layer.

摘要翻译： 一种制造混合集成电路的方法，该混合集成电路包括彼此相邻并连接到载体衬底（3）的半导体元件（1）和压电滤波器（2）。 半导体元件包括形成在硅层（13,28）中的半导体区域（5,6）。 压电滤波器包括位于声反射器层（7）上的声共振器（8,9,10），该谐振器包括一层压电材料（8），第一电极（9）位于第 压电材料和声反射器层，以及位于压电层的相对侧并面向第一电极的第二电极（10）。 在该方法中，半导体元件形成在硅晶片（12,25）的第一侧（11）上。 在该晶片的同一侧，形成压电材料层和第一电极，此后，表面被声反射层覆盖。 随后，使用粘合剂层（22）将由此形成的结构与声反射器层附接到载体基板。 最后，在滤光器的位置处，从晶片的第二侧去除硅，并且不需要对比较厚的声反射器进行图案化，使得在蚀刻所述反射器层期间底层特征不会被损坏。

公开(公告)号：US06775350B2

公开(公告)日：2004-08-10

申请号：US10242924

申请日：2002-09-13

申请人： Catharina Huberta Henrica Emons ,  Henricus Godefridus Rafael Maas ,  Theodorus Martinus Michielsen ,  Ronald Dekker ,  Antonius Johannes Janssen ,  Ingrid Annemarie Rink

发明人： Catharina Huberta Henrica Emons ,  Henricus Godefridus Rafael Maas ,  Theodorus Martinus Michielsen ,  Ronald Dekker ,  Antonius Johannes Janssen ,  Ingrid Annemarie Rink

IPC分类号： G01N2320

CPC分类号： G01N23/225 ,  G01N23/223 ,  G01N2223/076 ,  H01L22/12

摘要： A method of examining a wafer of crystalline semiconductor material by means of X-rays, in which method a surface of the wafer is scanned by means of an X-ray beam and secondary radiation generated by said X-ray beam is detected. Prior to the examination the surface of the wafer which is to be scanned by the X-ray beam during the examination is glued to a substrate, after which crystalline semiconductor material is removed at the side which is then exposed, removal taking place as far as the top layer which adjoins the surface. The top layer can thus be examined without the examination being affected by crystal defects or impurities present in layers of the wafer which are situated underneath the top layer.

摘要翻译： 通过X射线检查晶体半导体材料的晶片的方法，其中通过X射线束扫描晶片的表面，并且检测由所述X射线束产生的二次辐射。 在检查之前，将在检查期间由X射线束扫描的晶片的表面胶合到基底上，然后在暴露的一侧去除结晶半导体材料，然后将其移除至 邻接表面的顶层。 因此可以检查顶层，而不检查晶体缺陷或存在于位于顶层下方的晶片层中的杂质。

公开(公告)号：US06562694B2

公开(公告)日：2003-05-13

申请号：US09746027

申请日：2000-12-21

申请人： Ronald Dekker ,  Henricus Godefridus Rafael Maas ,  Cornelis Eustatius Timmering ,  Pascal Henri Leon Bancken

发明人： Ronald Dekker ,  Henricus Godefridus Rafael Maas ,  Cornelis Eustatius Timmering ,  Pascal Henri Leon Bancken

IPC分类号： H01L2176

CPC分类号： H01L21/76264 ,  H01L21/76283

摘要： A method of manufacturing a semiconductor device including semiconductor elements having semiconductor zones (17, 18, 24, 44, 45) formed in a top layer (4) of a silicon wafer (1) situated on a buried insulating layer (2). In this method, a first series of process steps are carried out, commonly referred to as front-end processing, wherein, inter alia, the silicon wafer is heated to temperatures above 700° C. Subsequently, trenches (25) are formed in the top layer, which extend as far as the buried insulating layer and do not intersect pn-junctions. After said trenches have been filled with insulating material (26, 29), the semiconductor device is completed in a second series of process steps, commonly referred to as back-end processing, wherein the temperature of the wafer does not exceed 400° C. The trenches are filled in a deposition process wherein the wafer is heated to a temperature which does not exceed 500° C. In this manner, a semiconductor device can be made comprising semiconductor elements having very small and shallow semiconductor zones.

摘要翻译： 一种制造半导体器件的方法，该半导体器件包括形成在位于掩埋绝缘层（2）上的硅晶片（1）的顶层（4）中的半导体区域（17,18,24,44,45）的半导体元件。 在该方法中，执行第一系列工艺步骤，通常称为前端处理，其中特别地，将硅晶片加热至高于700℃的温度。随后，形成沟槽（25） 顶层，其延伸至掩埋绝缘层并且不与pn结相交。 在所述沟槽已经填充有绝缘材料（26,29）之后，半导体器件在第二系列工艺步骤中完成，通常称为后端处理，其中晶片的温度不超过400℃。 在沉积工艺中填充沟槽，其中将晶片加热到不超过500℃的温度。以这种方式，可以制造半导体器件，其包括具有非常小且浅的半导体区域的半导体元件。

公开(公告)号：US07027269B2

公开(公告)日：2006-04-11

申请号：US09923611

申请日：2001-08-07

申请人： Frank Cornelis Penning ,  Ronald Dekker ,  Henricus Godefridus Rafael Maas

发明人： Frank Cornelis Penning ,  Ronald Dekker ,  Henricus Godefridus Rafael Maas

IPC分类号： G11B5/127

CPC分类号： G11B5/17 ,  G11B5/60 ,  G11B11/10534 ,  G11B11/10554 ,  G11B11/1058

摘要： A simple method of manufacturing a magnetic head having a head face and including a planar magnetic coil (7) which extends parallel to the head face. According to the method, the magnetic coil is formed at a first side of a first substrate (1). Thereafter, the first substrate provided with the magnetic coil is adhered with its first side to a side of a second substrate, whereafter material of the first substrate is removed from a second side of the first substrate (9), the second side being turned away from the first side, in order to form the head face, in such a manner that the magnetic coil is situated near to the head face.

摘要翻译： 一种制造具有头部表面并包括平行于头部表面延伸的平面磁性线圈（7）的磁头的简单方法。 根据该方法，在第一基板（1）的第一侧形成有电磁线圈。 此后，设置有磁性线圈的第一基板的第一侧粘附到第二基板的一侧，之后从第一基板（9）的第二侧去除第一基板的材料，将第二侧面转回 从第一侧开始，以使磁性线圈靠近头部表面的方式形成头部面。

公开(公告)号：US06698073B2

公开(公告)日：2004-03-02

申请号：US09790298

申请日：2001-02-21

申请人： Ronald Dekker ,  Henricus Godefridus Rafael Maas

发明人： Ronald Dekker ,  Henricus Godefridus Rafael Maas

IPC分类号： H04R1710

CPC分类号： H03H9/564 ,  H03H3/02 ,  H03H2003/025 ,  Y10T29/42 ,  Y10T29/49128 ,  Y10T29/49155

摘要： A method of manufacturing a piezoelectric filter with a resonator comprising a layer of a piezoelectric material (1) which is provided with an electrode (2,3) on either side, which resonator is situated on an acoustic reflector layer (4) formed on a surface (6) of a carrier substrate (7). In the method, the layer of piezoelectric material (1) is provided on a surface (8) of an auxiliary substrate (9), after which a first electrode (2) is formed on the layer of piezoelectric material (1). The acoustic reflector layer (4) is provided on and next to the first electrode (2), and the structure thus formed is secured with the side facing away from the auxiliary substrate (9) on the carrier substrate (7). The auxiliary substrate (9) is removed and a second electrode (3) situated opposite the first electrode (2) is provided.

摘要翻译： 一种制造具有谐振器的压电滤波器的方法，该谐振器包括在任一侧上设置有电极（2,3）的压电材料（1）的层，该谐振器位于形成在 载体基板（7）的表面（6）。 在该方法中，压电材料层（1）设置在辅助基板（9）的表面（8）上，之后在压电材料层（1）上形成第一电极（2）。 声反射器层（4）设置在第一电极（2）上并且紧邻第一电极（2），并且如此形成的结构被固定在载体基板（7）上的背离辅助基板（9）的一侧。 移除辅助基板（9），并且设置与第一电极（2）相对的第二电极（3）。

公开(公告)号：US06593628B2

公开(公告)日：2003-07-15

申请号：US09819280

申请日：2001-03-28

申请人： Ronald Dekker ,  Henricus Godefridus Rafael Maas ,  Jan Willem Slotboom ,  Freerk Van Rijs

发明人： Ronald Dekker ,  Henricus Godefridus Rafael Maas ,  Jan Willem Slotboom ,  Freerk Van Rijs

IPC分类号： H01L2701

CPC分类号： H01L27/0825 ,  H01L21/8222 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1203

摘要： The invention relates to an essentially discrete semiconductor device comprising a semiconductor body (10) having a first, preferably bipolar, transistor (T1) with a first region (1) forming a collector (1) of T1, and a second, preferably also bipolar, transistor (T2) with a second region (2) forming a collector (2) of T2, which transistors (T1, T2) are in a cascode configuration wherein the collector (1) of T1is connected to the emitter (4) of T2. Such a device cannot suitably be used in a base station for mobile communication. According to the invention, the first region (1) and the second region (2) are positioned next to each other within a semiconductor region (5), a part of which situated below the first region (1) is provided with a higher doping concentration at the location of T1. In this way, T1 has a low collector-emitter breakdown voltage and a high cutoff frequency, whereas for T2 said voltage and frequency are, respectively, high(er) and low(er). The resultant device is very suitable, on the one hand, for a high voltage application, for example 28 V, and a high power application, for example 100 W and, on the other hand, the device can still operate at a very high speed and hence is very suitable for the above application. Moreover, the device can be manufactured very easily using a method according to the invention. Preferably, the device is rendered suitable for surface mounting, and the semiconductor body is attached to an isolating substrate (20), while the parts thereof that are situated outside T1 and T2 are removed.

摘要翻译： 本发明涉及一种基本上分立的半导体器件，其包括具有第一优选为双极晶体管（T1）的半导体本体（10），其中第一区域（1）形成为T1的集电极（1），第二区域（1）优选为双极晶体管 ，具有形成T2的集电极（2）的第二区域（2）的晶体管（T2），所述晶体管（T1，T2）处于共源共栅结构，其中T1的集电极（1）连接到T2的发射极（4） 。 这样的设备不能适用于用于移动通信的基站。 根据本发明，第一区域（1）和第二区域（2）在半导体区域（5）内彼此相邻定位，其一部分位于第一区域（1）的下方，具有较高的掺杂 集中在T1的位置。 以这种方式，T1具有低集电极 - 发射极击穿电压和高截止频率，而对于T2，所述电压和频率分别为高（呃）和低（呃）。 一方面，所得到的装置非常适合于高压应用，例如28V，以及高功率应用，例如100W，另一方面，该装置仍然可以以非常高的速度运行 因此非常适合于上述应用。 此外，可以使用根据本发明的方法非常容易地制造该装置。 优选地，该装置适于表面安装，并且半导体主体附接到隔离衬底（20），而位于T1和T2外部的部分被去除。

公开(公告)号：US06762510B2

公开(公告)日：2004-07-13

申请号：US10140663

申请日：2002-05-08

申请人： Johann-Heinrich Fock ,  Wolfgang Schnitt ,  Hauke Pohlmann ,  Andreas Gakis ,  Michael Burnus ,  Martin Schaefer ,  Henricus Godefridus Rafael Maas ,  Theodorus Martinus Michielsen ,  Ronald Dekker

发明人： Johann-Heinrich Fock ,  Wolfgang Schnitt ,  Hauke Pohlmann ,  Andreas Gakis ,  Michael Burnus ,  Martin Schaefer ,  Henricus Godefridus Rafael Maas ,  Theodorus Martinus Michielsen ,  Ronald Dekker

IPC分类号： H01L2348

CPC分类号： H01L23/49855 ,  H01L23/5388 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A flexible monolithic integrated circuit which is essentially formed from flexible circuit elements, connecting elements between the flexible circuit elements, and a flexible coating which comprises at least one layer of a coating material comprising a polymer, is suitable as a small and convenient integrated circuit for electronic devices on flexible data carriers for the logistic tracking of objects and persons. The invention also relates to a method of manufacturing a flexible integrated monolithic circuit whereby integrated monolithic circuit elements and connecting elements are formed in and on a semiconductor substrate, the main surface of the integrated circuit elements facing away from the semiconductor substrate are coated with a polymer resin, and the semiconductor substrate is removed. The method is based on conventional process steps in semiconductor technology and leads to a flexible integrated monolithic circuit in a small number of process steps.

摘要翻译： 基本上由柔性电路元件形成的柔性单片集成电路，柔性电路元件之间的连接元件以及包括至少一层包含聚合物的涂层材料的柔性涂层，适合作为小型便利的集成电路 柔性数据载体上的电子设备用于对物体和人的物流跟踪。本发明还涉及一种制造柔性集成单体电路的方法，由此在半导体衬底内和半导体衬底上形成集成的单体电路元件和连接元件， 面向半导体衬底的集成电路元件被涂覆有聚合物树脂，并且去除半导体衬底。 该方法基于半导体技术中的常规工艺步骤，并且在少量工艺步骤中导致灵活的集成单片电路。

公开(公告)号：US06387769B2

公开(公告)日：2002-05-14

申请号：US09797086

申请日：2001-03-01

申请人： Ronald Dekker ,  Henricus Godefridus Rafael Maas ,  Anco Heringa ,  Holger Schligtenhorst

发明人： Ronald Dekker ,  Henricus Godefridus Rafael Maas ,  Anco Heringa ,  Holger Schligtenhorst

IPC分类号： H01L2120

CPC分类号： H01L29/66174 ,  H01L21/8222 ,  H01L27/0664 ,  H01L29/93

摘要： A method of producing a Schottky varicap (25) including: (a) providing an epitaxial layer (12) on a semiconductor substrate (1); (b) providing an insulating layer including an oxide layer and a nitride layer on a predetermined area of the surface of the epitaxial layer (12); (c) depositing a polysilicon layer (6); (d) applying a first high temperature step to diffuse a guard ring (10) around the first predetermined area; (e) removing a predetermined portion of the polysilicon layer (6) to expose the first silicon nitride film (5); (f) implanting atoms through at least the first oxide film (4) to provide a predetermined varicap doping profile; (g) applying a second high temperature step to anneal and activate the varicap doping profile; (h) removing the first oxide film (4) to provide an exposed area; (i) providing a Schottky electrode (17) on the exposed area.

摘要翻译： 一种制造肖特基变容二极管（25）的方法，包括：（a）在半导体衬底（1）上提供外延层（12）;（b）在预定区域上提供包括氧化物层和氮化物层的绝缘层 外延层（12）的表面;（c）沉积多晶硅层（6）;（d）施加第一高温步骤以使保护环（10）围绕第一预定区域扩散;（e） 多晶硅层（6）的一部分以暴露第一氮化硅膜（5）;（f）通过至少第一氧化物膜（4）注入原子以提供预定的变种胶料掺杂分布;（g）施加第二高温 步骤，退火并激活变种胶掺杂分布;（h）去除第一氧化膜（4）以提供暴露区域;（i）在暴露区域上提供肖特基电极（17）。

公开(公告)号：US07845378B2

公开(公告)日：2010-12-07

申请号：US11773149

申请日：2007-07-03

申请人： Henricus Godefridus Rafael Maas ,  Theodorus Martinus Michielsen ,  Richard Jozef Maria Waelen

发明人： Henricus Godefridus Rafael Maas ,  Theodorus Martinus Michielsen ,  Richard Jozef Maria Waelen

IPC分类号： B29C65/02

CPC分类号： C09J5/06 ,  C09J2400/143

摘要： A method for bonding two plate-shaped objects (5) with an adhesive which is cured by ultraviolet light irradiation and by heating. The two plate-shaped objects (5) with the adhesive in between are transported into a cure chamber (11) comprising an ultraviolet lamp (12) and a heating element (13). A movable heat-shielding member (3) is temporary present between the objects (5) and the heating element (13) during at least the first part of the irradiation treatment. Preferably, the heat-shielding member (3) is positioned outside the cure chamber (11) during a part of the cure treatment.

摘要翻译： 一种将两个板状物体（5）与通过紫外线照射和加热固化的粘合剂接合的方法。 具有粘合剂的两个板状物体（5）被输送到包括紫外灯（12）和加热元件（13）的固化室（11）中。 在照射处理的至少第一部分期间，可移动的热屏蔽构件（3）临时存在于物体（5）和加热元件（13）之间。 优选地，在固化处理的一部分期间，热屏蔽构件（3）位于固化室（11）的外部。

公开(公告)号：US06452272B1

公开(公告)日：2002-09-17

申请号：US09763841

申请日：2001-02-27

申请人： Henricus Godefridus Rafael Maas ,  Maria Henrica Wilhelmina Antonia Van Deurzen

发明人： Henricus Godefridus Rafael Maas ,  Maria Henrica Wilhelmina Antonia Van Deurzen

IPC分类号： H01L2348

CPC分类号： H01L23/642 ,  H01L23/4825 ,  H01L23/66 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/48463 ,  H01L2224/854 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01068 ,  H01L2924/04941 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A semiconductor device 1 comprises a body 2 of insulating material having a surface 3 to which a semiconductor element 4 and an interconnect structure 5 are fastened, which interconnect structure 5 is disposed between the semiconductor element 4 and the body 2 of insulating material and has a patterned metal layer 7 facing the body 2 of insulating material, which patterned metal layer 7 comprises conductor tracks 8 and 9. In order to reduce the power consumption of the semiconductor device 1, an insulating layer 12 having a dielectric constant ∈r below 3 is disposed between the patterned metal layer 7 of the interconnect structure 5 and the body 2 of insulating material, and an insulating barrier layer 13 is disposed between the semiconductor element 4 and the insulating layer 12 having a dielectric constant ∈r below 3, so as to counteract that contaminants from the insulating layer 12 having a dielectric constant ∈r below 3 can reach the semiconductor element 4.

摘要翻译： 半导体器件1包括具有半导体元件4和互连结构5的表面3的绝缘材料体2，该互连结构5设置在半导体元件4和绝缘材料体2之间，并且具有 图案化的金属层7面向绝缘材料的主体2，该图案化的金属层7包括导体轨道8和9.为了降低半导体器件1的功率消耗，介电常数εr低于3的绝缘层12是 布置在互连结构5的图案化金属层7和绝缘材料体2之间，绝缘阻挡层13设置在半导体元件4和介电常数εr低于3的绝缘层12之间，以便 抵消介电常数εr低于3的绝缘层12的污染物可以到达半导体元件4。