公开(公告)号：US5026657A

公开(公告)日：1991-06-25

申请号：US491784

申请日：1990-03-12

申请人： Ruojia Lee ,  Tyler A. Lowrey ,  Fernando Gonzalez ,  Joseph J. Karniewicz ,  Pierre C. Fazan

发明人： Ruojia Lee ,  Tyler A. Lowrey ,  Fernando Gonzalez ,  Joseph J. Karniewicz ,  Pierre C. Fazan

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/8242

CPC分类号： H01L27/10844 ,  H01L21/823835 ,  H01L29/665 ,  Y10S257/90

摘要： A split-polysilicon CMOS DRAM process incorporating self-aligned silicidation of the cell plate, transistor gates and N+ regions with a minimum of additional processing steps. By employing a light oxidation step to protect the P-channel transistor sidewall gates from silicidation during a subsequent processing step, the process avoids the problems that may be created by the double etching of the field oxide and active area regions that has heretofore been required for self-aligned silidation utilizing a split-polysilicon CMOS process. A protective nitride layer is used to prevent oxidation on those regions which are to be silicided. When this improved process is utilized for DRAM fabrication, the protective nitride layer may also be utilized as the cell dielectric. Although this process precludes the silicidation of the sources and drains of P-channel transistors, silicidation of other important regions is accomplished with very few steps required beyond those required for the basic split-polysilicon CMOS process without self-aligned silicidation of conductive regions.

摘要翻译： 分离多晶硅CMOS DRAM工艺，其结合了单元板，晶体管栅极和N +区域的自对准硅化，具有最小的附加处理步骤。 通过采用光氧化步骤来在随后的处理步骤期间保护P沟道晶体管侧壁栅极不被硅化，该过程避免了可能由现场氧化物和有源区域的双重蚀刻产生的问题， 利用分裂多晶硅CMOS工艺进行自对准硅化。 使用保护性氮化物层来防止要被硅化的那些区域上的氧化。 当这种改进的工艺用于DRAM制造时，保护性氮化物层也可以用作电池电介质。 尽管这个过程排除了P沟道晶体管的源极和漏极的硅化，但是除了不需要导电区域的自对准硅化的基本分裂多晶硅CMOS工艺所需要的步骤之外，其它重要区域的硅化是非常少的步骤。

公开(公告)号：US5013680A

公开(公告)日：1991-05-07

申请号：US555980

申请日：1990-07-18

申请人： Tyler A. Lowrey ,  Randal W. Chance ,  D. Mark Durcan ,  Ruojia Lee ,  Charles H. Dennison ,  Yauh-Ching Liu ,  Pierre C. Fazan ,  Fernando Gonzalez ,  Gordon A. Haller

发明人： Tyler A. Lowrey ,  Randal W. Chance ,  D. Mark Durcan ,  Ruojia Lee ,  Charles H. Dennison ,  Yauh-Ching Liu ,  Pierre C. Fazan ,  Fernando Gonzalez ,  Gordon A. Haller

IPC分类号： H01L21/033 ,  H01L21/308 ,  H01L21/334 ,  H01L21/336 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8242

CPC分类号： H01L27/10864 ,  H01L21/033 ,  H01L21/3086 ,  H01L21/76232 ,  H01L21/768 ,  H01L29/66181 ,  H01L29/66666 ,  Y10S438/947

摘要： A process for creating a DRAM array having feature widths that transcend the resolution limit of the employed photolithographic process using only five photomasking steps. The process involves the following steps: creation of a half-pitch hard-material mask that is used to etch a series of equidistanty-spaced isolation trenches in a silicon substrate; filling the isolation trenches with insulative material; creation of a hard-material mask consisting of strips that are 1-1/2F in width, separated by spaces that are 1/2F in width, that is used to etch a matrix of storage trenches; angled implantation of a N-type impurity in the storage trench walls; another anisotropic etch to deepen the storage trenches; deposition of a capacitor dielectric layer; deposition of a protective polysilicon layer on top of the dielectric layer; removal of the dielectric layer and the protective polysilicon layer at the bottom of each storage trench with a further anisotropic etch; filling the storage trenches with in-situ-doped polysilicon; planarization down to the substrate level; creation of an access gate on opposite sides of each storage trench, in addition to wordlines which interconnect gates within array columns by anisotropically etching a conformal conductive layer that has been deposited on top of oxide-silicon mesas that run perpendicular to the isolation trenches and are centered between the rows of storage trenches, the oxide-silicon mesas having been created with an etch using a photoresist mask consisting of a series of parallel strips that have been laid down with minimum feature and space width, then plasma etched to 3/4F; creation of source and drains with an N-type implant; and anisotropically etching the metal layer to create bitlines along the sidewalls of the oxide mesas.

摘要翻译： 一种用于创建DRAM阵列的方法，其具有仅使用五个光掩模步骤超越所使用的光刻工艺的分辨率极限的特征宽度。 该方法包括以下步骤：产生半间距硬材料掩模，其用于蚀刻硅衬底中的一系列等间隔隔开的隔离沟槽; 用绝缘材料填充隔离沟; 由宽度为1-1 / 2F的条形成的宽度为1 / 2F的间隔的用于蚀刻存储沟槽的矩阵的硬质材料掩模的形成; 在存储沟槽壁中倾斜注入N型杂质; 另一种各向异性蚀刻来加深存储沟槽; 沉积电容器电介质层; 保护性多晶硅层在电介质层的顶部上沉积; 通过进一步的各向异性蚀刻在每个存储沟槽的底部去除电介质层和保护性多晶硅层; 用原位掺杂多晶硅填充存储沟槽; 平坦化到底层水平; 在每个存储沟槽的相对侧上形成存取栅极，除了通过各向异性蚀刻已经沉积在垂直于隔离沟槽的氧化物 - 硅台面顶部上的共形导电层来互连阵列列内的栅极的字线之外，并且是 在存储沟槽的行之间居中，使用由具有最小特征和空间宽度放置的一系列平行条组成的光刻胶掩模，然后将等离子体蚀刻到3 / 4F，利用蚀刻产生氧化物 - 硅台面; 用N型植入物创建源和排水沟; 并各向异性地蚀刻金属层以沿着氧化物台面的侧壁产生位线。

公开(公告)号：US5177027A

公开(公告)日：1993-01-05

申请号：US569353

申请日：1990-08-17

申请人： Tyler A. Lowrey ,  Randal W. Chance ,  D. Mark Durcan ,  Pierre C. Fazan ,  Fernando Gonzalez ,  Gordon A. Haller

发明人： Tyler A. Lowrey ,  Randal W. Chance ,  D. Mark Durcan ,  Pierre C. Fazan ,  Fernando Gonzalez ,  Gordon A. Haller

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8242 ,  H01L29/423

CPC分类号： H01L29/66477 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/2815 ,  H01L21/31662 ,  H01L21/76237 ,  H01L27/10873 ,  H01L29/66666 ,  H01L29/4236

摘要： A process for fabricating, on the more or less vertical edge of a silicon mesa, a MOS field-effect transistor which has a spacer-shaped gate and a right-angled channel path. The process involves the following steps: creating a raised region (the mesa) on a planar silicon substrate; creation of a gate oxide layer on the substrate and vertical sidewalls of the mesa; blanket deposition of a gate layer (typically polysilicon); anisotropically etching the gate layer to expose the upper surface of the mesa and leave a stringer gate around the circumference thereof; and doping the upper surface of the mesa and regions of the substrate peripheral to the circumferential polysilicon stringer to create source and drain regions. The standard process provides device density approximately double that of standard FET fabrication processes. Density can be increased even further by increasing the number of silicon mesas with a minimum pitch distance. This may be accomplished by employing the reduced-pitch masking technique disclosed in a copending U.S. patent application. Multiple transistors may be created on a single mesa by creating isolation regions within the mesa. The circumferential gate may be severed so as to provide a pair of gate inputs for transistors created on a single mesa. Enhancements common to conventional MOSFETS, such as lightly-doped source and drains, halos, etc., may be utilized for the new MOSFET process.

摘要翻译： 在硅台面的或多或少垂直边缘上制造具有间隔物形栅极和直角沟道路径的MOS场效应晶体管的工艺。 该方法包括以下步骤：在平面硅衬底上产生凸起区域（台面）; 在基板上形成栅极氧化物层和台面的垂直侧壁; 栅极层（通常为多晶硅）的覆盖沉积; 各向异性地蚀刻栅极层以暴露台面的上表面并且围绕其周边留下纵梁; 并且将周向多晶硅桁条外围的台面的上表面和基板的区域掺杂以产生源区和漏区。 标准工艺提供的器件密度约为标准FET制造工艺的两倍。 通过增加具有最小间距距离的硅台面的数量，可进一步增加密度。 这可以通过采用共同未决的美国专利申请中公开的减少节距掩蔽技术来实现。 可以通过在台面内创建隔离区域，在单个台面上创建多个晶体管。 可以切断周向栅极，以便为在单个台面上产生的晶体管提供一对栅极输入。 对于新的MOSFET工艺，可以使用传统MOSFETs通用的增强功能，例如轻掺杂源极和漏极，卤素等。

公开(公告)号：US5057449A

公开(公告)日：1991-10-15

申请号：US498669

申请日：1990-03-26

申请人： Tyler A. Lowrey ,  Fernando Gonzalez ,  Joseph J. Karniewicz

发明人： Tyler A. Lowrey ,  Fernando Gonzalez ,  Joseph J. Karniewicz

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/32 ,  H01L21/8234 ,  H01L21/8242

CPC分类号： H01L27/10873 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28167 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/823462 ,  H01L21/28211 ,  Y10S148/163

摘要： A process for creating two thicknesses or gate oxide within a dynamic random memory. The process begins by thermally growing a first layer of gate oxide on a silicon substrate. This first layer is then masked with photoresist in regions where cell access transistors will ultimately be fabricated. All oxide that is not masked is then removed with an oxide etch. After the photoresist is stripped, a second layer of gate oxide is thermally grown on the substrate. The resultant oxided layer, which comprises multiple-thickness components, is used as a pad oxide layer during a conventional LOCOS operation. Peripheral driver transistors are construction on top of a thin layer of gate oxide so as to optimize their performance, whereas, cell access transistors are constructed on top of a thicker layer of gate oxide so as to minimize row line capacitance. A net increase in row line access speed is thus obtained.

摘要翻译： 在动态随机存储器内创建两个厚度或栅极氧化物的工艺。 该过程开始于在硅衬底上热生长第一层栅极氧化物。 然后在最终将制造单元存取晶体管的区域中用光致抗蚀剂掩蔽该第一层。 然后用氧化物蚀刻去除未被掩蔽的全部氧化物。 在剥离光致抗蚀剂之后，在衬底上热生长第二层栅氧化层。 在常规LOCOS操作期间，将包含多个厚度成分的所得氧化层用作衬垫氧化物层。 外围驱动器晶体管是在栅极氧化物的薄层之上构建的，以便优化其性能，而单元存取晶体管构造在较厚的栅极氧化物层之上，以便使行线电容最小化。 从而获得行线访问速度的净增加。

公开(公告)号：US5252504A

公开(公告)日：1993-10-12

申请号：US835003

申请日：1992-02-11

申请人： Tyler A. Lowrey ,  Fernando Gonzalez ,  Ruojia Lee

发明人： Tyler A. Lowrey ,  Fernando Gonzalez ,  Ruojia Lee

IPC分类号： H01L21/8242 ,  H01L27/105 ,  H01L27/108 ,  H01L21/336

CPC分类号： H01L27/10844 ,  H01L27/10805 ,  H01L27/105

摘要： A CMOS integrated circuit such as a DRAM is fabricated, in which a first layer of polysilicon is used to form transistor gates, and capacitor cell plates are formed from a second polysilicon layer.N-wells are first formed, followed by initial oxide. The application of the CMOS process to the reverse poly technique provides enhanced alignment of critical transistor gates and permits the use of less mask steps in fabricating the CMOS circuit.

摘要翻译： 制造诸如DRAM的CMOS集成电路，其中第一层多晶硅用于形成晶体管栅极，并且电容器单元板由第二多晶硅层形成。 首先形成N阱，然后是初始氧化物。 将CMOS工艺应用于反向多晶技术提供关键晶体管栅极的增强的对准，并且允许在制造CMOS电路中使用较少的掩模步骤。

公开(公告)号：US5134085A

公开(公告)日：1992-07-28

申请号：US796099

申请日：1991-11-21

申请人： Brent D. Gilgen ,  Tyler A. Lowrey ,  Joseph J. Karniewicz ,  Anthony M. McQueen

发明人： Brent D. Gilgen ,  Tyler A. Lowrey ,  Joseph J. Karniewicz ,  Anthony M. McQueen

IPC分类号： H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10852

摘要： This invention constitutes a 10-12 mask, split-polysilicon process for fabricating dynamic random access memories of the stacked capacitor type for the one-megabit generation and beyond. The process flow is characterized: reduced mask count due to the elimination of the N+ and p+ source-drain masking layers via the split polysilicon technique; an option to further reduce wafer processing by allowing the LOCOS stress relief (pad) oxide layer to later function as the transistor gate dielectric layer; N-channel device optimization via self-aligned punch-through and lightly-doped-drain (LDD) implants, without the addition of extra P-channel masking steps via the split poly approach; use of semi, self-aligned contact of bottom cell plate to access gate diffusion allowing tight spacing between bottom cell plate buried contact and access gate polysilicon; improved refresh characteristics achieved by avoiding reduction of isolation thickness due to the spacer oxide etch; improved refresh characteristics achieved by protecting the sensitive areas of the storage node from damage typically caused by a spacer oxide etch; improved refresh characteristics achieved by eliminating the high-dose N-channel source/drain implantation from the storage node side of the access transistor gate; and improved immunity to soft error upset achieved through the use of an optional self-aligned "Hi-C" implant that is performed without the addition of an extra masking step.

摘要翻译： 本发明构成了用于制造用于1兆比特或更大的叠层电容器类型的动态随机存取存储器的10-12掩模，分裂多晶硅工艺。 工艺流程的特征在于：通过分离多晶硅技术消除N +和p +源极 - 漏极掩蔽层，减少掩模计数; 通过允许LOCOS应力消除（焊盘）氧化物层稍后用作晶体管栅极介电层来进一步减少晶片加工的选择; 通过自对准穿通和轻掺杂漏极（LDD）种植体进行N沟道器件优化，而不需要通过分裂聚合法添加额外的P沟道掩蔽步骤; 使用底部单元板的半自动对准接触来访问栅极扩散，允许底部单元板掩埋触点和存取栅极多晶硅之间的紧密间隔; 通过避免由于间隔氧化物蚀刻而导致的隔离厚度的降低而获得的改进的刷新特性; 通过保护存储节点的敏感区域免受通常由间隔物氧化物蚀刻引起的损坏而实现的改善的刷新特性; 通过从存取晶体管栅极的存储节点侧消除高剂量N沟道源极/漏极注入而获得的改善的刷新特性; 并且通过使用在不添加额外掩蔽步骤的情况下执行的可选择的自对准“Hi-C”植入物来实现对软错误不舒服的改善的免疫力。

公开(公告)号：US5126290A

公开(公告)日：1992-06-30

申请号：US760026

申请日：1991-09-11

申请人： Tyler A. Lowrey ,  Ruojia Lee

发明人： Tyler A. Lowrey ,  Ruojia Lee

IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L21/8246 ,  H01L23/525

CPC分类号： H01L27/11206 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/31612 ,  H01L21/76802 ,  H01L21/76888 ,  H01L23/5252 ,  H01L2924/0002 ,  Y10S257/90

摘要： The present invention provides a programmable structure for a programmable read-only memory (PROM) which utilizes one-sided ozone spacers constructed on the digit lines as one time programmable nodes. An oxide/nitride/oxide layer (ONO) is used as an interface between underlying parallel rows of digit lines, having one-sided ozone spacers, and overlying parallel columns of word lines in a programmable read only memory. With a each digit line passing under each word line in a row/column matrix is formed thereby providing a programmable digit/word line matrix. Each crossing point of the digit and word lines in the matrix will be permanently programmed to either a one or a zero by rupturing the thin ONO dielectric interface by applying the appropriate voltage potential between the associated digit/word line conductors.

摘要翻译： 本发明提供了一种用于可编程只读存储器（PROM）的可编程结构，该可编程只读存储器利用在数字线上构造的单面臭氧间隔作为一次可编程节点。 氧化物/氮化物/氧化物层（ONO）用作下列平行的数字行行之间的接口，具有单面臭氧间隔物，并且在可编程只读存储器中覆盖字线的平行列。 通过在行/列矩阵中的每个字线下方通过的每个数字线形成，从而提供可编程数字/字线矩阵。 矩阵中的数字和字线的每个交叉点将通过在相关联的数字/字线导体之间施加适当的电压电位来破坏薄ONO电介质接口而被永久编程为一个或零。

公开(公告)号：US5286993A

公开(公告)日：1994-02-15

申请号：US855810

申请日：1992-03-23

申请人： Tyler A. Lowrey ,  Ruojia Lee

发明人： Tyler A. Lowrey ,  Ruojia Lee

IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L21/8246 ,  H01L23/525 ,  H01L27/02 ,  G11C17/00

CPC分类号： H01L27/11206 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/31612 ,  H01L21/76802 ,  H01L21/76888 ,  H01L23/5252 ,  H01L2924/0002 ,  Y10S257/90

摘要： The present invention provides a programmable structure for a programmable read-only memory (PROM) which utilizes one-sided ozone spacers constructed on the digit lines as one time programmable nodes. An oxide/nitride/oxide layer (ONO) is used as an interface between underlying parallel rows of digit lines, having one-sided ozone spacers, and overlying parallel columns of word lines in a programmable read only memory With a each digit line passing under each word line in a row/column matrix is formed thereby providing a programmable digit/word line matrix. Each crossing point of the digit and word lines in the matrix will be permanently programmed to either a one or a zero by rupturing the thin ONO dielectric interface by applying the appropriate voltage potential between the associated digit/word line conductors.

摘要翻译： 本发明提供了一种用于可编程只读存储器（PROM）的可编程结构，该可编程只读存储器利用在数字线上构造的单面臭氧间隔作为一次可编程节点。 氧化物/氮化物/氧化物层（ONO）用作下列平行的数字行行之间的接口，具有单面臭氧间隔物，并且在可编程只读存储器中覆盖字线的并行列，每个数字线通过 形成行/列矩阵中的每个字线，从而提供可编程数字/字线矩阵。 矩阵中的数字和字线的每个交叉点将通过在相关联的数字/字线导体之间施加适当的电压电位来破坏薄ONO电介质接口而被永久编程为一个或一个零。

公开(公告)号：US5069747A

公开(公告)日：1991-12-03

申请号：US633573

申请日：1990-12-21

申请人： David A. Cathey ,  Mark E. Tuttle ,  Ruojia Lee ,  Tyler A. Lowrey

发明人： David A. Cathey ,  Mark E. Tuttle ,  Ruojia Lee ,  Tyler A. Lowrey

IPC分类号： H01L21/033 ,  H01L21/266 ,  H01L21/316 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/0337 ,  H01L21/266 ,  H01L21/31612 ,  H01L29/6656

摘要： A process for creating and removing temporary silicon dioxide structures on an in-process integrated circuit with minimal effect on existing permanent silicon dioxide structures that are exposed. The process comprises the steps of blanket depositing an ozone-TEOS silicon dioxide layer through chemical vapor deposition on top of the in-process integrated circuit, thus covering permanent structures formed from conventional silicon dioxides (e.g. TEOS and thermal oxides), etching the ozone-TEOS layer to create said temporary structures, and removing the temporary structures using dilute hydrofluoric acid.

摘要翻译： 一种用于在过程中集成电路中创建和去除临时二氧化硅结构的方法，对暴露的现有永久性二氧化硅结构的影响最小。 该方法包括以下步骤：通过化学气相沉积在过程中集成电路的顶部覆盖沉积臭氧-TEOS二氧化硅层，从而覆盖由常规二氧化硅（例如TEOS和热氧化物）形成的永久结构， TEOS层以产生所述临时结构，并使用稀氢氟酸除去临时结构。

公开(公告)号：US5331196A

公开(公告)日：1994-07-19

申请号：US114886

申请日：1993-08-31

申请人： Tyler A. Lowrey ,  Ruojia Lee

发明人： Tyler A. Lowrey ,  Ruojia Lee

IPC分类号： G11C17/16 ,  H01L27/112

CPC分类号： G11C17/16 ,  H01L27/112

摘要： A one-time, voltage-programmable, logic element has an antifuse element constructed within a trench etched in a silicon substrate. A sidewall of the trench abuts a diffusion region. The trench is lined with a nitride dielectric layer, which is in turn covered by polycrystalline silicon. The polycrystalline silicon serves as a voltage reference line. In a preferred embodiment, the diffusion region forms a first source/drain region of a field-effect transistor. In order to program the element, a voltage sufficient to rupture the nitride dielectric layer is applied between the diffusion region and the reference line. The transistor is utilized to isolate a particular logic element from other logic elements.

摘要翻译： 一次性电压可编程逻辑元件具有构造在蚀刻在硅衬底中的沟槽内的反熔丝元件。 沟槽的侧壁邻接扩散区域。 沟槽衬有氮化物介电层，其又由多晶硅覆盖。 多晶硅用作电压参考线。 在优选实施例中，扩散区域形成场效应晶体管的第一源极/漏极区域。 为了对元件进行编程，在扩散区和参考线之间施加足以破坏氮化物电介质层的电压。 晶体管用于将特定逻辑元件与其他逻辑元件隔离。