公开(公告)号：US5013680A

公开(公告)日：1991-05-07

申请号：US555980

申请日：1990-07-18

申请人： Tyler A. Lowrey ,  Randal W. Chance ,  D. Mark Durcan ,  Ruojia Lee ,  Charles H. Dennison ,  Yauh-Ching Liu ,  Pierre C. Fazan ,  Fernando Gonzalez ,  Gordon A. Haller

发明人： Tyler A. Lowrey ,  Randal W. Chance ,  D. Mark Durcan ,  Ruojia Lee ,  Charles H. Dennison ,  Yauh-Ching Liu ,  Pierre C. Fazan ,  Fernando Gonzalez ,  Gordon A. Haller

IPC分类号： H01L21/033 ,  H01L21/308 ,  H01L21/334 ,  H01L21/336 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8242

CPC分类号： H01L27/10864 ,  H01L21/033 ,  H01L21/3086 ,  H01L21/76232 ,  H01L21/768 ,  H01L29/66181 ,  H01L29/66666 ,  Y10S438/947

摘要： A process for creating a DRAM array having feature widths that transcend the resolution limit of the employed photolithographic process using only five photomasking steps. The process involves the following steps: creation of a half-pitch hard-material mask that is used to etch a series of equidistanty-spaced isolation trenches in a silicon substrate; filling the isolation trenches with insulative material; creation of a hard-material mask consisting of strips that are 1-1/2F in width, separated by spaces that are 1/2F in width, that is used to etch a matrix of storage trenches; angled implantation of a N-type impurity in the storage trench walls; another anisotropic etch to deepen the storage trenches; deposition of a capacitor dielectric layer; deposition of a protective polysilicon layer on top of the dielectric layer; removal of the dielectric layer and the protective polysilicon layer at the bottom of each storage trench with a further anisotropic etch; filling the storage trenches with in-situ-doped polysilicon; planarization down to the substrate level; creation of an access gate on opposite sides of each storage trench, in addition to wordlines which interconnect gates within array columns by anisotropically etching a conformal conductive layer that has been deposited on top of oxide-silicon mesas that run perpendicular to the isolation trenches and are centered between the rows of storage trenches, the oxide-silicon mesas having been created with an etch using a photoresist mask consisting of a series of parallel strips that have been laid down with minimum feature and space width, then plasma etched to 3/4F; creation of source and drains with an N-type implant; and anisotropically etching the metal layer to create bitlines along the sidewalls of the oxide mesas.

摘要翻译： 一种用于创建DRAM阵列的方法，其具有仅使用五个光掩模步骤超越所使用的光刻工艺的分辨率极限的特征宽度。 该方法包括以下步骤：产生半间距硬材料掩模，其用于蚀刻硅衬底中的一系列等间隔隔开的隔离沟槽; 用绝缘材料填充隔离沟; 由宽度为1-1 / 2F的条形成的宽度为1 / 2F的间隔的用于蚀刻存储沟槽的矩阵的硬质材料掩模的形成; 在存储沟槽壁中倾斜注入N型杂质; 另一种各向异性蚀刻来加深存储沟槽; 沉积电容器电介质层; 保护性多晶硅层在电介质层的顶部上沉积; 通过进一步的各向异性蚀刻在每个存储沟槽的底部去除电介质层和保护性多晶硅层; 用原位掺杂多晶硅填充存储沟槽; 平坦化到底层水平; 在每个存储沟槽的相对侧上形成存取栅极，除了通过各向异性蚀刻已经沉积在垂直于隔离沟槽的氧化物 - 硅台面顶部上的共形导电层来互连阵列列内的栅极的字线之外，并且是 在存储沟槽的行之间居中，使用由具有最小特征和空间宽度放置的一系列平行条组成的光刻胶掩模，然后将等离子体蚀刻到3 / 4F，利用蚀刻产生氧化物 - 硅台面; 用N型植入物创建源和排水沟; 并各向异性地蚀刻金属层以沿着氧化物台面的侧壁产生位线。

公开(公告)号：US5252504A

公开(公告)日：1993-10-12

申请号：US835003

申请日：1992-02-11

申请人： Tyler A. Lowrey ,  Fernando Gonzalez ,  Ruojia Lee

发明人： Tyler A. Lowrey ,  Fernando Gonzalez ,  Ruojia Lee

IPC分类号： H01L21/8242 ,  H01L27/105 ,  H01L27/108 ,  H01L21/336

CPC分类号： H01L27/10844 ,  H01L27/10805 ,  H01L27/105

摘要： A CMOS integrated circuit such as a DRAM is fabricated, in which a first layer of polysilicon is used to form transistor gates, and capacitor cell plates are formed from a second polysilicon layer.N-wells are first formed, followed by initial oxide. The application of the CMOS process to the reverse poly technique provides enhanced alignment of critical transistor gates and permits the use of less mask steps in fabricating the CMOS circuit.

摘要翻译： 制造诸如DRAM的CMOS集成电路，其中第一层多晶硅用于形成晶体管栅极，并且电容器单元板由第二多晶硅层形成。 首先形成N阱，然后是初始氧化物。 将CMOS工艺应用于反向多晶技术提供关键晶体管栅极的增强的对准，并且允许在制造CMOS电路中使用较少的掩模步骤。

公开(公告)号：US5026657A

公开(公告)日：1991-06-25

申请号：US491784

申请日：1990-03-12

申请人： Ruojia Lee ,  Tyler A. Lowrey ,  Fernando Gonzalez ,  Joseph J. Karniewicz ,  Pierre C. Fazan

发明人： Ruojia Lee ,  Tyler A. Lowrey ,  Fernando Gonzalez ,  Joseph J. Karniewicz ,  Pierre C. Fazan

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/8242

CPC分类号： H01L27/10844 ,  H01L21/823835 ,  H01L29/665 ,  Y10S257/90

摘要： A split-polysilicon CMOS DRAM process incorporating self-aligned silicidation of the cell plate, transistor gates and N+ regions with a minimum of additional processing steps. By employing a light oxidation step to protect the P-channel transistor sidewall gates from silicidation during a subsequent processing step, the process avoids the problems that may be created by the double etching of the field oxide and active area regions that has heretofore been required for self-aligned silidation utilizing a split-polysilicon CMOS process. A protective nitride layer is used to prevent oxidation on those regions which are to be silicided. When this improved process is utilized for DRAM fabrication, the protective nitride layer may also be utilized as the cell dielectric. Although this process precludes the silicidation of the sources and drains of P-channel transistors, silicidation of other important regions is accomplished with very few steps required beyond those required for the basic split-polysilicon CMOS process without self-aligned silicidation of conductive regions.

摘要翻译： 分离多晶硅CMOS DRAM工艺，其结合了单元板，晶体管栅极和N +区域的自对准硅化，具有最小的附加处理步骤。 通过采用光氧化步骤来在随后的处理步骤期间保护P沟道晶体管侧壁栅极不被硅化，该过程避免了可能由现场氧化物和有源区域的双重蚀刻产生的问题， 利用分裂多晶硅CMOS工艺进行自对准硅化。 使用保护性氮化物层来防止要被硅化的那些区域上的氧化。 当这种改进的工艺用于DRAM制造时，保护性氮化物层也可以用作电池电介质。 尽管这个过程排除了P沟道晶体管的源极和漏极的硅化，但是除了不需要导电区域的自对准硅化的基本分裂多晶硅CMOS工艺所需要的步骤之外，其它重要区域的硅化是非常少的步骤。

公开(公告)号：US5126290A

公开(公告)日：1992-06-30

申请号：US760026

申请日：1991-09-11

申请人： Tyler A. Lowrey ,  Ruojia Lee

发明人： Tyler A. Lowrey ,  Ruojia Lee

IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L21/8246 ,  H01L23/525

CPC分类号： H01L27/11206 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/31612 ,  H01L21/76802 ,  H01L21/76888 ,  H01L23/5252 ,  H01L2924/0002 ,  Y10S257/90

摘要： The present invention provides a programmable structure for a programmable read-only memory (PROM) which utilizes one-sided ozone spacers constructed on the digit lines as one time programmable nodes. An oxide/nitride/oxide layer (ONO) is used as an interface between underlying parallel rows of digit lines, having one-sided ozone spacers, and overlying parallel columns of word lines in a programmable read only memory. With a each digit line passing under each word line in a row/column matrix is formed thereby providing a programmable digit/word line matrix. Each crossing point of the digit and word lines in the matrix will be permanently programmed to either a one or a zero by rupturing the thin ONO dielectric interface by applying the appropriate voltage potential between the associated digit/word line conductors.

摘要翻译： 本发明提供了一种用于可编程只读存储器（PROM）的可编程结构，该可编程只读存储器利用在数字线上构造的单面臭氧间隔作为一次可编程节点。 氧化物/氮化物/氧化物层（ONO）用作下列平行的数字行行之间的接口，具有单面臭氧间隔物，并且在可编程只读存储器中覆盖字线的平行列。 通过在行/列矩阵中的每个字线下方通过的每个数字线形成，从而提供可编程数字/字线矩阵。 矩阵中的数字和字线的每个交叉点将通过在相关联的数字/字线导体之间施加适当的电压电位来破坏薄ONO电介质接口而被永久编程为一个或零。

公开(公告)号：US5286993A

公开(公告)日：1994-02-15

申请号：US855810

申请日：1992-03-23

申请人： Tyler A. Lowrey ,  Ruojia Lee

发明人： Tyler A. Lowrey ,  Ruojia Lee

IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L21/8246 ,  H01L23/525 ,  H01L27/02 ,  G11C17/00

CPC分类号： H01L27/11206 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/31612 ,  H01L21/76802 ,  H01L21/76888 ,  H01L23/5252 ,  H01L2924/0002 ,  Y10S257/90

摘要： The present invention provides a programmable structure for a programmable read-only memory (PROM) which utilizes one-sided ozone spacers constructed on the digit lines as one time programmable nodes. An oxide/nitride/oxide layer (ONO) is used as an interface between underlying parallel rows of digit lines, having one-sided ozone spacers, and overlying parallel columns of word lines in a programmable read only memory With a each digit line passing under each word line in a row/column matrix is formed thereby providing a programmable digit/word line matrix. Each crossing point of the digit and word lines in the matrix will be permanently programmed to either a one or a zero by rupturing the thin ONO dielectric interface by applying the appropriate voltage potential between the associated digit/word line conductors.

摘要翻译： 本发明提供了一种用于可编程只读存储器（PROM）的可编程结构，该可编程只读存储器利用在数字线上构造的单面臭氧间隔作为一次可编程节点。 氧化物/氮化物/氧化物层（ONO）用作下列平行的数字行行之间的接口，具有单面臭氧间隔物，并且在可编程只读存储器中覆盖字线的并行列，每个数字线通过 形成行/列矩阵中的每个字线，从而提供可编程数字/字线矩阵。 矩阵中的数字和字线的每个交叉点将通过在相关联的数字/字线导体之间施加适当的电压电位来破坏薄ONO电介质接口而被永久编程为一个或一个零。

公开(公告)号：US5069747A

公开(公告)日：1991-12-03

申请号：US633573

申请日：1990-12-21

申请人： David A. Cathey ,  Mark E. Tuttle ,  Ruojia Lee ,  Tyler A. Lowrey

发明人： David A. Cathey ,  Mark E. Tuttle ,  Ruojia Lee ,  Tyler A. Lowrey

IPC分类号： H01L21/033 ,  H01L21/266 ,  H01L21/316 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/0337 ,  H01L21/266 ,  H01L21/31612 ,  H01L29/6656

摘要： A process for creating and removing temporary silicon dioxide structures on an in-process integrated circuit with minimal effect on existing permanent silicon dioxide structures that are exposed. The process comprises the steps of blanket depositing an ozone-TEOS silicon dioxide layer through chemical vapor deposition on top of the in-process integrated circuit, thus covering permanent structures formed from conventional silicon dioxides (e.g. TEOS and thermal oxides), etching the ozone-TEOS layer to create said temporary structures, and removing the temporary structures using dilute hydrofluoric acid.

摘要翻译： 一种用于在过程中集成电路中创建和去除临时二氧化硅结构的方法，对暴露的现有永久性二氧化硅结构的影响最小。 该方法包括以下步骤：通过化学气相沉积在过程中集成电路的顶部覆盖沉积臭氧-TEOS二氧化硅层，从而覆盖由常规二氧化硅（例如TEOS和热氧化物）形成的永久结构， TEOS层以产生所述临时结构，并使用稀氢氟酸除去临时结构。

公开(公告)号：US5331196A

公开(公告)日：1994-07-19

申请号：US114886

申请日：1993-08-31

申请人： Tyler A. Lowrey ,  Ruojia Lee

发明人： Tyler A. Lowrey ,  Ruojia Lee

IPC分类号： G11C17/16 ,  H01L27/112

CPC分类号： G11C17/16 ,  H01L27/112

摘要： A one-time, voltage-programmable, logic element has an antifuse element constructed within a trench etched in a silicon substrate. A sidewall of the trench abuts a diffusion region. The trench is lined with a nitride dielectric layer, which is in turn covered by polycrystalline silicon. The polycrystalline silicon serves as a voltage reference line. In a preferred embodiment, the diffusion region forms a first source/drain region of a field-effect transistor. In order to program the element, a voltage sufficient to rupture the nitride dielectric layer is applied between the diffusion region and the reference line. The transistor is utilized to isolate a particular logic element from other logic elements.

摘要翻译： 一次性电压可编程逻辑元件具有构造在蚀刻在硅衬底中的沟槽内的反熔丝元件。 沟槽的侧壁邻接扩散区域。 沟槽衬有氮化物介电层，其又由多晶硅覆盖。 多晶硅用作电压参考线。 在优选实施例中，扩散区域形成场效应晶体管的第一源极/漏极区域。 为了对元件进行编程，在扩散区和参考线之间施加足以破坏氮化物电介质层的电压。 晶体管用于将特定逻辑元件与其他逻辑元件隔离。

公开(公告)号：US5241496A

公开(公告)日：1993-08-31

申请号：US746824

申请日：1991-08-19

申请人： Tyler A. Lowrey ,  Ruojia Lee

发明人： Tyler A. Lowrey ,  Ruojia Lee

IPC分类号： G11C17/16 ,  H01L27/112

CPC分类号： G11C17/16 ,  H01L27/112

摘要： A one-time, voltage-programmable, read-only memory array in which individual memory cells comprise an insulated-gate, field-effect transistor, the channel of which provides, through a voltage-programmable anti-fuse element, a current path between a reference voltage line and a bitline. In a preferred embodiment, the array comprises a semiconductor substrate having a series of parallel, alternating, minimum-pitch field isolation region and active area strips, a series of parallel, minimum-pitch wordlines overlying and perpendicular to the field isolation region and active area strips, the wordlines being insulated from the active areas by a gate dielectric layer and being dielectrically insulated on their edges and upper surfaces, source/drain junction regions between each wordline pair and field isolation strip pair, a reference voltage line between and coextensive with every other wordline pair that makes anti-fuseable contact to each subjacent pair of cell junctions along its length, antifuseable contact for each cell being made within a trench that extends below junction depth, and is lined with conformal silicon nitride dielectric layer that breaks down when subjected to a programming voltage. A series of minimum pitch bitlines, which run parallel to the wordlines, completes the memory array. Each bitline makes direct contact with each pair of cell junctions along its length. The array is characterized by a non-folded bitline architecture.

公开(公告)号：US5122848A

公开(公告)日：1992-06-16

申请号：US682623

申请日：1991-04-08

申请人： Ruojia Lee ,  Fernando Gonzalez

发明人： Ruojia Lee ,  Fernando Gonzalez

IPC分类号： H01L21/336 ,  H01L21/8242 ,  H01L29/78

CPC分类号： H01L27/10864 ,  H01L29/66666 ,  H01L29/7827

摘要： An insulated-gate vertical FET has a channel region and gate structure that is formed along the sidewall of trench in a P-type semiconductor substrate. The drain and source regions of the FET are formed in the mesa and the base portions of the trench. All contacts to the gate, drain, and source regions can be made from the top surface of the semiconductor substrate. One or more sidewalls of the trench are oxidized with a thin gate oxide dielectric layer followed by a thin polysilicon deposited film to form an insulated gate layer. A reactive ion etch step removes the insulated gate layer from the mesa and the base portion of the trench. An enhanced N-type implant creates the drain and source regions in the mesa and the base portions of the trench. The trench is partially filled with a spacer oxide layer to reduce gate-to-source overlap capacitance. A conformal conductive polysilicon layer is deposited over the insulated gate layer. A portion of the conductive polysilicon layer is extended above the surface of the trench onto the mesa to form a gate contact. A field oxide covers the entire surface of the FET, which is opened in the mesa to form gate and drain contacts, and in the base to form the source contact.

摘要翻译： 绝缘栅垂直FET具有在P型半导体衬底中沿着沟槽的侧壁形成的沟道区和栅极结构。 FET的漏极和源极区域形成在沟槽的台面和基部中。 可以从半导体衬底的顶表面制造到栅极，漏极和源极区域的所有接触。 沟槽的一个或多个侧壁用薄的栅极氧化物介电层氧化，随后是薄的多晶硅沉积膜以形成绝缘的栅极层。 反应离子蚀刻步骤从绝缘栅极层和沟槽的基底部分去除绝缘栅极层。 增强的N型注入器在沟槽的台面和基部中产生漏极和源极区域。 沟槽部分地填充有间隔氧化物层以减少栅极到源极重叠电容。 在绝缘栅极层上沉积保形导电多晶硅层。 导电多晶硅层的一部分在沟槽的表面上延伸到台面上以形成栅极接触。 场氧化物覆盖FET的整个表面，其在台面中打开以形成栅极和漏极接触，并且在基底中形成源极接触。

公开(公告)号：US5037773A

公开(公告)日：1991-08-06

申请号：US612296

申请日：1990-11-08

申请人： Ruojia Lee ,  Fernando Gonzalez

发明人： Ruojia Lee ,  Fernando Gonzalez

IPC分类号： H01L21/02 ,  H01L21/3215

CPC分类号： H01L28/84 ,  H01L21/32155 ,  Y10S148/133

摘要： A technique for effectively doping a storage node capacitor plate constructed from low temperature deposited rugged polysilicon. A phosphorus silica glass is deposited prior polysilicon deposition and used primarily to uniformly diffuse n-type dopants into the subsequently deposited rugged poly capacitor plate. This doping technique eliminates the need for high temperature doping and will maintain the rugged surface in the poly of the capacitor plate.

摘要翻译： 一种有效掺杂由低温沉积的多晶硅构成的存储节点电容器板的技术。 在多晶硅沉积之前沉积磷石英玻璃，并主要用于将n型掺杂剂均匀地扩散到随后沉积的耐久性多晶硅电容器板中。 该掺杂技术消除了对高温掺杂的需要，并且将保持电容器板的多晶硅中的粗糙表面。