公开(公告)号：US20100307684A1

公开(公告)日：2010-12-09

申请号：US12680321

申请日：2008-09-26

申请人： Ryosaku Ota ,  Hikaru Adachi ,  Toshio Nakanishi ,  Atsushi Ueda ,  Songyun Kang ,  Paul Moroz ,  Peter Ventzek

发明人： Ryosaku Ota ,  Hikaru Adachi ,  Toshio Nakanishi ,  Atsushi Ueda ,  Songyun Kang ,  Paul Moroz ,  Peter Ventzek

IPC分类号： H01L21/306

CPC分类号： H05H1/46 ,  H01J37/32192 ,  H01J37/3222 ,  H01J37/32229

摘要： A microwave plasma processing apparatus (100) of a slot antenna type includes a plane antenna plate (31) constituting a flat waveguide and a cover (34) of a conductive member. The cover (34) is provided with a stub (43) as a second waveguide for adjusting electric field-distribution in the flat waveguide. The stub (43) is provided in the cover (34) of the conductive member. In plan view, the stub (43) is arranged to overlap slots (32) constituting a slot pair arranged at the outermost circumference of the plane antenna plate (31). By appropriately arranging the stub, it is possible to control electric field-distribution in the flat waveguide thereby to generate a uniform plasma.

摘要翻译： 缝隙天线类型的微波等离子体处理装置（100）包括构成平坦波导的平面天线板（31）和导电部件的盖（34）。 盖34具有作为调整平面波导中的电场分布的第二波导的短截线43。 短路（43）设置在导电构件的盖（34）中。 在平面图中，短截线体43被布置成与构成设置在平面天线板31的最外圆周处的缝隙对的缝隙重叠。 通过适当地布置短截线，可以控制平坦波导中的电场分布，从而产生均匀的等离子体。

公开(公告)号：US08636871B2

公开(公告)日：2014-01-28

申请号：US12523212

申请日：2007-12-27

申请人： Ikuo Sawada ,  Peter Ventzek ,  Tatsuro Ohshita ,  Kazuyoshi Matsuzaki ,  Songyun Kang

发明人： Ikuo Sawada ,  Peter Ventzek ,  Tatsuro Ohshita ,  Kazuyoshi Matsuzaki ,  Songyun Kang

IPC分类号： C23F1/00 ,  H01L21/306 ,  C23C16/00

CPC分类号： H01J37/32568 ,  H01J37/32082 ,  H01J37/32091 ,  H01J37/3244 ,  H01J37/32522 ,  H01J37/32541

摘要： A plasma processing apparatus includes a first electrode and a second electrode so arranged in the upper portion of a processing chamber as to face a mounting table, a gas supply unit for supplying a processing gas between the first electrode and the second electrode, a RF power supply unit for applying a RF power between the first electrode and the second electrode for converting the process gas supplied between the electrodes into a plasma, and a gas exhaust unit for evacuating the inside of the processing chamber to a vacuum level from the lower portion of the processing chamber. Since the electron temperature in the plasma is low near a substrate on the mounting table, damage to the substrate caused by the plasma can be suppressed. In addition, since a metal can be used as a material for the processing chamber, the processing chamber can have good temperature controllability.

摘要翻译： 等离子体处理装置包括：第一电极和第二电极，其布置在处理室的上部面对安装台;气体供应单元，用于在第一电极和第二电极之间提供处理气体; RF功率 供给单元，用于在第一电极和第二电极之间施加RF电力，用于将在电极之间供应的处理气体转换成等离子体;以及气体排出单元，用于将处理室的内部从下部 处理室。 由于等离子体中的电子温度在安装台上的基板附近低，所以可以抑制由等离子体引起的对基板的损伤。 此外，由于金属可以用作处理室的材料，处理室可以具有良好的温度可控性。

公开(公告)号：US20100006543A1

公开(公告)日：2010-01-14

申请号：US12523212

申请日：2007-12-27

申请人： Ikuo Sawada ,  Peter Ventzek ,  Tatsuro Ohshita ,  Kazuyoshi Matsuzaki ,  Songyun Kang

发明人： Ikuo Sawada ,  Peter Ventzek ,  Tatsuro Ohshita ,  Kazuyoshi Matsuzaki ,  Songyun Kang

IPC分类号： C23F1/00 ,  C23C16/00 ,  C23F1/08 ,  C23C16/505

CPC分类号： H01J37/32568 ,  H01J37/32082 ,  H01J37/32091 ,  H01J37/3244 ,  H01J37/32522 ,  H01J37/32541

摘要： A plasma processing apparatus includes a first electrode and a second electrode so arranged in the upper portion of a processing chamber as to face a mounting table, a gas supply unit for supplying a processing gas between the first electrode and the second electrode, a RF power supply unit for applying a RF power between the first electrode and the second electrode for converting the process gas supplied between the electrodes into a plasma, and a gas exhaust unit for evacuating the inside of the processing chamber to a vacuum level from the lower portion of the processing chamber. Since the electron temperature in the plasma is low near a substrate on the mounting table, damage to the substrate caused by the plasma can be suppressed. In addition, since a metal can be used as a material for the processing chamber, the processing chamber can have good temperature controllability.

摘要翻译： 等离子体处理装置包括：第一电极和第二电极，其布置在处理室的上部面对安装台;气体供应单元，用于在第一电极和第二电极之间提供处理气体; RF功率 供给单元，用于在第一电极和第二电极之间施加RF电力，用于将在电极之间供应的处理气体转换成等离子体;以及气体排出单元，用于将处理室的内部从下部 处理室。 由于等离子体中的电子温度在安装台上的基板附近低，所以可以抑制由等离子体引起的对基板的损伤。 此外，由于金属可以用作处理室的材料，处理室可以具有良好的温度可控性。

公开(公告)号：US20070231946A1

公开(公告)日：2007-10-04

申请号：US11240241

申请日：2005-09-30

申请人： Marius Orlowski ,  Shahid Rauf ,  Peter Ventzek

发明人： Marius Orlowski ,  Shahid Rauf ,  Peter Ventzek

IPC分类号： H01L51/40 ,  H01L51/00 ,  H01L35/24 ,  H01L29/08

CPC分类号： H01L21/76838 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/89 ,  Y10S977/891 ,  Y10S977/932 ,  Y10S977/939 ,  H01L2924/00

摘要： A semiconductor device has lateral conductors or traces that are formed of nanotubes such as carbon. A sacrificial layer is formed overlying the substrate. A dielectric layer is formed overlying the sacrificial layer. A lateral opening is formed by removing a portion of the dielectric layer and the sacrificial layer which is located between two columns of metallic catalysts. The lateral opening includes a neck portion and a cavity portion which is used as a constrained space to grow a nanotube. A plasma is used to apply electric charge that forms an electric field which controls the direction of formation of the nanotubes. Nanotubes from each column of metallic catalyst are laterally grown and either abut or merge into one nanotube. Contact to the nanotube may be made from either the neck portion or the columns of metallic catalysts.

摘要翻译： 半导体器件具有由碳纳米管形成的横向导体或迹线。 覆盖衬底上形成牺牲层。 覆盖在牺牲层上的电介质层。 通过去除位于两列金属催化剂之间的介电层和牺牲层的一部分来形成侧向开口。 横向开口包括颈部和空腔部分，其用作用于生长纳米管的约束空间。 使用等离子体来施加形成控制纳米管形成方向的电场的电荷。 来自每列金属催化剂的纳米管横向生长并邻接或合并成一个纳米管。 与纳米管的接触可以由金属催化剂的颈部或者柱子制成。

公开(公告)号：US20110017706A1

公开(公告)日：2011-01-27

申请号：US12668106

申请日：2008-07-10

申请人： Tetsuro Takahashi ,  Yutaka Fujino ,  Hiroyuki Toshima ,  Atsushi Kubo ,  Song Yun Kang ,  Peter Ventzek ,  Sumie Segawa

发明人： Tetsuro Takahashi ,  Yutaka Fujino ,  Hiroyuki Toshima ,  Atsushi Kubo ,  Song Yun Kang ,  Peter Ventzek ,  Sumie Segawa

IPC分类号： C23F1/08 ,  C23C16/50 ,  C23F1/00 ,  C23C16/511 ,  C23C16/00

CPC分类号： H01L21/3145 ,  H01J37/32192 ,  H01J37/3222 ,  H01L21/02247 ,  H01L21/02332 ,  H01L21/318 ,  H01L21/67069 ,  H01L21/68735 ,  H01L21/68742

摘要： A wafer is disposed in a chamber, a plasma generating space is formed in the chamber, plasma processing is performed to the front surface of the processing object while keeping at least the front surface of the processing object in contact with the plasma generating space. The plasma processing is performed with the plasma generating space being kept in contact with at least the peripheral region of the back surface of the processing object.

摘要翻译： 将晶片设置在室中，在室内形成等离子体产生空间，同时至少使处理对象的前表面与等离子体产生空间保持接触，对处理对象的前表面进行等离子体处理。 等离子体处理是在等离子体产生空间与加工对象的后表面的至少周边区域保持接触的情况下进行的。

公开(公告)号：US20050164514A1

公开(公告)日：2005-07-28

申请号：US10766205

申请日：2004-01-28

申请人： Shahid Rauf ,  Peter Ventzek ,  Wei Wu

发明人： Shahid Rauf ,  Peter Ventzek ,  Wei Wu

IPC分类号： G03F1/00 ,  H01L21/302 ,  H01L21/311

CPC分类号： G03F1/34 ,  H01L21/31116

摘要： A chromeless phase lithography mask (30) that does not require photoresist to manufacture has a quartz substrate (32) is etched by using a plasma (38) containing one of a nitrogen augmented hydro-fluorocarbon oxygen mixture and a nitrogen augmented fluorocarbon oxygen mixture. Various hydro-fluorocarbons or fluorocarbons may be used. The nitrogen addition results in etched openings in the quartz substrate that have substantially vertical sidewalls in a uniform manner across the substrate. Surface roughness is minimized and edges of the openings are well-defined with minimal rounding. The etch rate is rendered controllable by reducing bias power without degrading a desired vertical sidewall profile.

公开(公告)号：US20070166973A1

公开(公告)日：2007-07-19

申请号：US11331786

申请日：2006-01-13

申请人： Shahid Rauf ,  Olubunmi Adetutu ,  Eric Luckowski ,  Peter Ventzek

发明人： Shahid Rauf ,  Olubunmi Adetutu ,  Eric Luckowski ,  Peter Ventzek

IPC分类号： H01L21/467

CPC分类号： H01L21/02071 ,  H01L21/28088 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/32139 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518

摘要： A metal layer etch process deposits, patterns and anisotropically etches a polysilicon layer (24) down to an underlying metal layer (22) to form an etched polysilicon structure (54) with polymer layers (50, 52) formed on its sidewall surfaces. The polymer layer (50, 52) are removed to expose an additional surface area (60, 62) of the metal layer (22), and dielectric layers (80, 82) are formed on the sidewall surfaces of the etched polysilicon structure (54). Next, the metal layer (22) is plasma etched to form an etched metal layer (95) with substantially vertical sidewall surfaces (97, 99) by simultaneously charging the dielectric layers (80, 82) to change plasma ion trajectories near the dielectric layers (80, 82) so that plasma ions (92, 94) impact the sidewall surfaces (97, 99) in a more perpendicular angle to enhance etching of the sidewall surfaces (97, 99) of the etched metal layer (95).

摘要翻译： 金属层蚀刻工艺沉积，图案和各向异性地将多晶硅层（24）向下蚀刻到下面的金属层（22）以形成蚀刻的多晶硅结构（54），其上形成有在其侧壁表面上的聚合物层（50,52）。 去除聚合物层（50,52）以暴露金属层（22）的另外的表面区域（60,62），并且在蚀刻的多晶硅结构（54）的侧壁表面上形成介电层（80,82） ）。 接下来，通过同时对电介质层（80,82）充电以改变电介质层附近的等离子体离子轨迹，等离子体蚀刻金属层（22）以形成具有基本上垂直的侧壁表面（97,99）的蚀刻金属层（95） （80,82），使得等离子体离子（92,94）以更垂直的角度冲击侧壁表面（97,99）以增强蚀刻金属层（95）的侧壁表面（97,99）的蚀刻。

公开(公告)号：US20070049048A1

公开(公告)日：2007-03-01

申请号：US11216254

申请日：2005-08-31

申请人： Shahid Rauf ,  Peter Ventzek

发明人： Shahid Rauf ,  Peter Ventzek

IPC分类号： H01L21/31

CPC分类号： H01L21/02247 ,  H01J37/3266 ,  H01J2237/3387 ,  H01L21/02252 ,  H01L21/28185 ,  H01L21/3144

摘要： A semiconductor manufacturing apparatus and process for forming a nitrided dielectric film includes generating a plasma source (44) over a wafer structure (46), where the plasma source (44) includes neutral species (such as nitrogen atoms) and charged species (such as nitrogen ions) that are formed in an inductively coupled plasma reactor. Before the charged species in the plasma (44) can penetrate the wafer structure (46), an electrically connected mesh structure (45, 47) between the plasma source (44) and wafer structure (46) blocks the charged species. In addition or in the alternative, a magnetic field (69) aligned in parallel with the surface of the wafer structure (66) is established in close proximity to the wafer structure (66) in order to trap the charged species. By removing charged species, an improved, narrower nitrogen concentration profile is obtained.

摘要翻译： 用于形成氮化电介质膜的半导体制造装置和工艺包括在晶片结构（46）上产生等离子体源（44），其中等离子体源（44）包括中性物质（例如氮原子）和带电物质（例如 氮离子），其形成在电感耦合等离子体反应器中。 在等离子体（44）中的带电物质可以穿透晶片结构（46）之前，等离子体源（44）和晶片结构（46）之间的电连接的网状结构（45,47）阻挡带电物质。 另外或在替代方案中，与晶片结构（66）的表面平行排列的磁场（69）被建立成靠近晶片结构（66）以捕获带电物质。 通过去除带电物质，获得了改进的较窄的氮浓度分布。

公开(公告)号：US20060063392A1

公开(公告)日：2006-03-23

申请号：US10945319

申请日：2004-09-20

申请人： Peter Ventzek ,  Kurt Junker ,  Marius Orlowski

发明人： Peter Ventzek ,  Kurt Junker ,  Marius Orlowski

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02112 ,  B82Y10/00 ,  H01L21/02282 ,  H01L21/318 ,  H01L21/76801 ,  H01L21/76813 ,  H01L21/76819 ,  H01L21/7682 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a dielectric layer is disclosed herein. In accordance with the method, a first material is provided (303) which comprises a suspension of nanoparticles in a liquid medium. A dielectric layer is then formed (305) on the substrate from the suspension through an evaporative process.

摘要翻译： 本文公开了形成电介质层的方法。 根据该方法，提供第一材料（303），其包括纳米颗粒在液体介质中的悬浮液。 然后通过蒸发过程从悬浮液在基底上形成介电层（305）。

公开(公告)号：US20050196961A1

公开(公告)日：2005-09-08

申请号：US10795847

申请日：2004-03-08

申请人： Da Zhang ,  Olubunmi Adetutu ,  Shahid Rauf ,  Peter Ventzek

发明人： Da Zhang ,  Olubunmi Adetutu ,  Shahid Rauf ,  Peter Ventzek

IPC分类号： H01L21/336 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L29/78

摘要： In one embodiment, a top surface of a semiconductor device (18) is amorphized in a tool (1). A metal is deposited over the semiconductor substrate using the same tool. In one embodiment, the same chambers are used. In an embodiment, the tool is a sputtering tool, such as a physical vapor deposition (PVD). The semiconductor substrate may be annealed to form a metal silicide (122) over at least a portion of the semiconductor device that includes silicon.

摘要翻译： 在一个实施例中，半导体器件（18）的顶表面在工具（1）中非晶化。 使用相同的工具在半导体衬底上沉积金属。 在一个实施例中，使用相同的腔室。 在一个实施例中，该工具是溅射工具，例如物理气相沉积（PVD）。 半导体衬底可以被退火以在包括硅的半导体器件的至少一部分上形成金属硅化物（122）。