PRINTED CIRCUIT BOARD AND A SEMICONDUCTOR PACKAGE INCLUDING THE SAME

    公开(公告)号:US20230292439A1

    公开(公告)日:2023-09-14

    申请号:US17954603

    申请日:2022-09-28

    CPC classification number: H05K1/181 H05K1/115

    Abstract: A printed circuit board includes a substrate structure including a first insulating material, a plurality of first wiring layers disposed on or in the first insulating material, and a plurality of first via layers disposed in the first insulating material; and an interconnect structure including a second insulating material, a plurality of second wiring layers disposed on or in the second insulating material, and one or more second via layers disposed in the second insulating material. The interconnect structure is disposed on an upper side of the substrate structure. The interconnect structure includes first and second connection regions. The first and second connection regions are spaced apart from each other.

    PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF

    公开(公告)号:US20200214135A1

    公开(公告)日:2020-07-02

    申请号:US16812640

    申请日:2020-03-09

    Abstract: There is provided a printed circuit board including: a first insulating layer; a first circuit pattern formed on a first surface of the first insulating layer; an adhesive layer provided on a second surface of the first insulating layer; and an electronic component disposed on the adhesive layer and enclosed by the first insulating layer and a second insulating layer formed on the first insulating layer.

    FAN-OUT SENSOR PACKAGE
    7.
    发明申请

    公开(公告)号:US20190229055A1

    公开(公告)日:2019-07-25

    申请号:US16107727

    申请日:2018-08-21

    Abstract: A fan-out sensor package includes: a first semiconductor chip module including a first connection member having a first through-hole and a first wiring layer, a first semiconductor chip disposed in the first through-hole and having an active surface on which a sensing region and first connection pads are disposed, and an encapsulant encapsulating at least portions of the first connection member and the first semiconductor chip and filling at least portions of the first through-hole; a redistribution module having a second through-hole exposing at least a portion of the sensing region and including a redistribution layer; and electrical connection structures electrically connecting the first wiring layer and the first connection pads to the redistribution layer.

    FAN-OUT SEMICONDUCTOR PACKAGE
    9.
    发明申请

    公开(公告)号:US20190164863A1

    公开(公告)日:2019-05-30

    申请号:US16000094

    申请日:2018-06-05

    Abstract: A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole and including an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, a second connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the semiconductor chip, and an encapsulant encapsulating the semiconductor chip and having a cavity disposed above the inactive surface of the semiconductor chip.

    ANTENNA MODULE AND MANUFACTURING METHOD THEREOF

    公开(公告)号:US20190027804A1

    公开(公告)日:2019-01-24

    申请号:US15958489

    申请日:2018-04-20

    Abstract: An antenna module includes a connection member including at least one wiring layer and at least one insulating layer; an integrated circuit (IC) disposed on a first surface of the connection member and electrically connected to the at least one wiring layer; and a plurality of antenna cells each disposed on a second surface of the connection member. Each of the plurality of antenna cells includes an antenna member configured to transmit or receive a radio frequency (RF) signal, a feed via having one end electrically connected to the antenna member and the other end electrically connected to a corresponding wire of the at least one wiring layer, a dielectric layer surrounding side surfaces of the feed via and having a height greater than that of the at least one insulating layer, and a plating member surrounding side surfaces of the dielectric layer.

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