Abstract:
A printed circuit board includes a substrate structure including a first insulating material, a plurality of first wiring layers disposed on or in the first insulating material, and a plurality of first via layers disposed in the first insulating material; and an interconnect structure including a second insulating material, a plurality of second wiring layers disposed on or in the second insulating material, and one or more second via layers disposed in the second insulating material. The interconnect structure is disposed on an upper side of the substrate structure. The interconnect structure includes first and second connection regions. The first and second connection regions are spaced apart from each other.
Abstract:
Aboard for an electronic component package includes a wiring part on which an electronic component is disposed, wherein the wiring part includes an insulating layer, a signal transferring wiring electrically connected to the electronic component, and an electrical testing wiring electrically disconnected from the electronic component, and the electrical testing wiring includes conductive patterns formed on both surfaces of the wiring part, and conductive vias electrically connecting the conductive patterns to each other.
Abstract:
There are provided a printed circuit board, a method of manufacturing the same, and an electronic component module. The printed circuit board comprises a first circuit layer; a first insulating layer formed to cover a portion or all of the first circuit layer; a second circuit layer formed on the first insulating layer; a second insulating layer formed on an overall surface of the board so as to cover the first circuit layer and the second circuit layer; and a third circuit layer formed in the second insulating layer. The second circuit layer has a circuit pattern of a fine pitch as compared to the first circuit layer and the third circuit layer.
Abstract:
There are provided a printed circuit board and a method of manufacturing the same. The printed circuit board include a glass plate, an insulating member penetrating through the glass plate, insulating layers disposed on a first surface and a second surface of the glass plate, and a via through the insulating member.
Abstract:
A printed circuit board includes a first circuit pattern embedded in an insulating layer so that an upper surface of the first circuit pattern is exposed to one surface of the insulating layer, a coupling pad embedded in the insulating layer to come into contact with a lower surface of the first circuit pattern, and a bump pad formed on the upper surface of the first circuit pattern to protrude from one surface of the insulating layer.
Abstract:
There is provided a printed circuit board including: a first insulating layer; a first circuit pattern formed on a first surface of the first insulating layer; an adhesive layer provided on a second surface of the first insulating layer; and an electronic component disposed on the adhesive layer and enclosed by the first insulating layer and a second insulating layer formed on the first insulating layer.
Abstract:
A fan-out sensor package includes: a first semiconductor chip module including a first connection member having a first through-hole and a first wiring layer, a first semiconductor chip disposed in the first through-hole and having an active surface on which a sensing region and first connection pads are disposed, and an encapsulant encapsulating at least portions of the first connection member and the first semiconductor chip and filling at least portions of the first through-hole; a redistribution module having a second through-hole exposing at least a portion of the sensing region and including a redistribution layer; and electrical connection structures electrically connecting the first wiring layer and the first connection pads to the redistribution layer.
Abstract:
A fan-out semiconductor package includes first and second structures. The first structure includes a first semiconductor chip, a first encapsulant, and a connection member. The second structure includes a second semiconductor chip, a second encapsulant, and conductive bumps. The first and second structures are disposed so that active surfaces of the first and second semiconductor chips face each other. The conductive bumps are electrically connected to a redistribution layer, and connection pads of the first and second semiconductor chips are connected to each other through the redistribution layer in a signal manner. Signal transmission times between one point of the redistribution layer and connection pads of each of the first and second semiconductor chips are substantially the same as each other.
Abstract:
A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole and including an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, a second connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the semiconductor chip, and an encapsulant encapsulating the semiconductor chip and having a cavity disposed above the inactive surface of the semiconductor chip.
Abstract:
An antenna module includes a connection member including at least one wiring layer and at least one insulating layer; an integrated circuit (IC) disposed on a first surface of the connection member and electrically connected to the at least one wiring layer; and a plurality of antenna cells each disposed on a second surface of the connection member. Each of the plurality of antenna cells includes an antenna member configured to transmit or receive a radio frequency (RF) signal, a feed via having one end electrically connected to the antenna member and the other end electrically connected to a corresponding wire of the at least one wiring layer, a dielectric layer surrounding side surfaces of the feed via and having a height greater than that of the at least one insulating layer, and a plating member surrounding side surfaces of the dielectric layer.