FAN-OUT SEMICONDUCTOR PACKAGE
    3.
    发明申请

    公开(公告)号:US20180145036A1

    公开(公告)日:2018-05-24

    申请号:US15655668

    申请日:2017-07-20

    摘要: A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole of the first connection member, the semiconductor chip including an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, a passive component attached to the active surface of the semiconductor chip, an encapsulant encapsulating at least a portion of the first connection member and the inactive surface of the semiconductor chip, and a second connection member disposed on the first connection member and the active surface of the semiconductor chip, the first connection member and the second connection member each including at least one redistribution layer electrically connected to the connection pads of the semiconductor chip, and the passive component being electrically connected to the connection pads of the semiconductor chip through the redistribution layer of the second connection member.

    ELECTRONIC COMPONENT EMBEDDED PRINTED CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME
    5.
    发明申请
    ELECTRONIC COMPONENT EMBEDDED PRINTED CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    电子元件嵌入式印刷电路板及其制造方法

    公开(公告)号:US20150096789A1

    公开(公告)日:2015-04-09

    申请号:US14272961

    申请日:2014-05-08

    发明人: Moon Il KIM

    摘要: The present invention relates to an electronic component embedded printed circuit board and a method for manufacturing the same.An electronic component embedded printed circuit board of the present invention includes a core having a cavity therein and internal circuit layers on upper and lower surfaces thereof; an electronic component inserted in the cavity and having an elastic body on an outer peripheral surface thereof; insulating layers laminated on the top and bottom of the core; external circuit layers patterned on the insulating layers; and vias formed in the insulating layers to electrically connect the internal circuit layers and the external circuit layers, wherein among the vias, the via in contact with the electronic component is connected through the elastic body.

    摘要翻译: 本发明涉及电子元件嵌入式印刷电路板及其制造方法。 本发明的电子部件嵌入式印刷电路板包括其内部具有空腔的芯和其上表面和下表面上的内部电路层; 电子部件,其插入到所述空腔中,并且在其外周面上具有弹性体; 绝缘层层压在芯的顶部和底部; 图案化在绝缘层上的外部电路层; 以及形成在绝缘层中的通孔,以电连接内部电路层和外部电路层,其中在通孔中,与电子部件接触的通孔通过弹性体连接。

    SEMICONDUCTOR PACKAGE AND ANTENNA MODULE INCLUDING THE SAME

    公开(公告)号:US20200373244A1

    公开(公告)日:2020-11-26

    申请号:US16556816

    申请日:2019-08-30

    摘要: A semiconductor package includes a frame having first and second through-portions, first and second semiconductor chips, respectively in the first and second through-portions, each having a first surface, on which a connection pad is disposed, a first encapsulant covering at least a portion of the first and second semiconductor chips, a first connection member on the first and second semiconductor chips including a first redistribution layer electrically connected to the connection pads of the first and second semiconductor chips and a heat dissipation pattern layer, at least one passive component above the first semiconductor chip on the first connection member, and at least one heat dissipation structure above the second semiconductor chip on the first connection member and connected to the heat dissipation pattern layer.

    SEMICONDUCTOR PACKAGE
    7.
    发明申请

    公开(公告)号:US20200321257A1

    公开(公告)日:2020-10-08

    申请号:US16513193

    申请日:2019-07-16

    摘要: A semiconductor package may include a frame including an insulation layer having a cavity formed in a lower surface of the insulation layer, a first post and a second post spaced apart from the cavity, and a metal plate disposed on an upper side of the cavity; a semiconductor chip having a first surface on which a connection pad is disposed and a second surface opposing the first surface; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure disposed on the frame and the first surface of the semiconductor chip, and including one or more redistribution layers. The first post is electrically connected to the wiring layer of the frame and the redistribution layer of the connection structure, and the second post is spaced apart from the first post.