中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

8 records (took 0.032 seconds)

    Image sensor with dummy lines for minimizing fixed pattern noise (FPN) and electronic apparatus including the same
    1.
    发明授权
    Image sensor with dummy lines for minimizing fixed pattern noise (FPN) and electronic apparatus including the same 有权

    公开(公告)号：US11031430B2

    公开(公告)日：2021-06-08

    申请号：US16045985

    申请日：2018-07-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jae-kyu Lee ,  Young-chan Kim ,  Seung-sik Kim

    IPC: H01L27/146 ,  H01L23/48 ,  H04N5/365

    Abstract: An image sensor and an electronic apparatus, the image sensor including a plurality of pixels, each pixel of the plurality of pixels including a photodiode and a transfer transistor, a reset transistor, a source-follower transistor, and a selection transistor, which correspond to the photodiode; a plurality of first interconnection lines connected to gates of the transfer transistor, the reset transistor, and the selection transistor, the plurality of first interconnection lines extending in a first direction; and a plurality of second interconnection lines connected to a source region of the selection transistor, the plurality of second interconnection lines extending in a second direction that intersects the first direction, wherein the plurality of second interconnection lines includes dummy lines on a peripheral area that is outside of a pixel area in which the pixels are located.

    Image Sensors Having a Reduced Settling Time
    2.
    发明申请
    Image Sensors Having a Reduced Settling Time 审中-公开

    公开(公告)号：US20190131332A1

    公开(公告)日：2019-05-02

    申请号：US16108613

    申请日：2018-08-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-kyu Lee ,  Hyuk-Soon Choi ,  Seung-sik Kim

    IPC: H01L27/146 ,  H04N5/369

    Abstract: Image sensors are provided including a structure capable of settling an output voltage within a very short time for implementing a high-speed image sensor. The image sensor includes a pixel area, in which a photo-diode (PD) and a transfer transistor (Tr) configured to transmit charges accumulated in the PD to a floating diffusion (FD) area are disposed; and a Tr area, which is disposed adjacent to the pixel area and includes a first Tr, a second Tr, and a third Tr, wherein a first gate oxide film disposed below a first gate electrode of the first Tr and a second gate oxide film disposed below a second gate electrode of the second Tr include channel oxide films thinner than a gate oxide film of the transfer Tr.

    Image sensor device
    3.
    发明授权
    Image sensor device 有权

    公开(公告)号：US11380722B2

    公开(公告)日：2022-07-05

    申请号：US16591059

    申请日：2019-10-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Min-Woong Seo ,  JungChak Ahn ,  Jae-kyu Lee

    IPC: H01L27/146 ,  H04N5/335 ,  H01L27/108 ,  H04N5/355 ,  H04N5/357

    Abstract: An image sensor device includes a digital pixel that includes a photo detector, a comparator, and a memory circuit, a pixel driver that controls the digital pixel, and a digital logic circuit that performs a digital signal processing operation on a digital signal output from the digital pixel. The photo detector and a first portion of the comparator are formed in a first semiconductor die, a second portion of the comparator, the memory circuit, and the pixel driver are formed in a second semiconductor die under the first semiconductor die, and the digital logic circuit is formed in a third semiconductor die under the second semiconductor die.

    Magnetic memory device
    5.
    发明授权
    Magnetic memory device 有权
    磁存储器件

    公开(公告)号：US09281344B2

    公开(公告)日：2016-03-08

    申请号：US14599064

    申请日：2015-01-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-kyu Lee ,  Ki-Seok Suh

    IPC: H01L29/82 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

    CPC classification number: H01L27/228 ,  G11C11/1659 ,  H01L43/02 ,  H01L43/08

    Abstract: The magnetic memory device includes a plurality of source lines arranged in parallel in a second direction orthogonal to a first direction while extending in the first direction on a substrate, a plurality of word lines arranged in parallel in the first direction while extending in the second direction on the substrate, a plurality of bit lines arranged in parallel in the second direction while extending in the first direction on the substrate to alternate with the plurality of source lines, and a plurality of active regions arranged to extend at an oblique angle with respect to the first direction and arranged so that one memory cell is selected when one of the plurality of word lines and one of the plurality of source lines or the plurality of bit lines are selected.

    Abstract translation: 磁存储器件包括沿与第一方向正交的第二方向平行布置的多条源极线，同时在衬底上沿第一方向延伸;多条字线，沿第一方向平行布置，同时沿第二方向延伸 在所述基板上，沿着所述第一方向在所述基板上沿所述第一方向延伸而与所述多个源极线交替的多个位线，所述多个位线在所述第二方向上平行布置，并且所述多个有源区域被布置成相对于 所述第一方向被布置成使得当所述多条字线中的一条字线和所述多条源极线或多条位线中的一条被选择时选择一个存储器单元。

    Resistive memory device capable of improving sensing margin of data
    7.
    发明授权
    Resistive memory device capable of improving sensing margin of data 有权
    能够提高数据传感距离的电阻式存储器件

    公开(公告)号：US09324382B2

    公开(公告)日：2016-04-26

    申请号：US14510629

    申请日：2014-10-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ki-Seok Suh ,  Jae-kyu Lee

    IPC: G11C5/08 ,  G11C11/16

    CPC classification number: G11C5/08 ,  G11C5/063 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1659 ,  G11C13/0023 ,  G11C2213/71 ,  H01L27/228

    Abstract: A resistive memory device includes a cell block having a plurality of unit memory cells in which a resistive element and a cell select element are connected to each other in series, the cell block operating in response to a word line, a bit line, and a source line, and a dummy line, when different interconnection layers form the source line and the bit line, respectively, connected to one of the interconnection layers which is formed at a lower side the remaining interconnection layer between the interconnection layers for the source line and the bit line, wherein the dummy line has a resistance lower than a resistance of the lower interconnection layer.

    Abstract translation: 电阻式存储器件包括具有多个单元存储器单元的单元块，其中电阻元件和单元选择元件串联连接在一起，所述单元块响应于字线，位线和 源极线和虚拟线，当不同的互连层分别形成源极线和位线时，分别与形成在源极线的互连层之间的剩余互连层的下侧形成的互连层之一连接， 位线，其中虚线具有比下互连层的电阻低的电阻。

Patent Agency Ranking