公开(公告)号：US20160211188A1

公开(公告)日：2016-07-21

申请号：US14808596

申请日：2015-07-24

Applicant: SK hynix Inc.

Inventor： Dae Woong LEE ,  Tae Min KANG ,  Han Jun BAE

IPC: H01L23/29 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/293 ,  H01L21/563 ,  H01L23/296 ,  H01L23/3142 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/04042 ,  H01L2224/26145 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83365 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/92247 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/181 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/0715

Abstract: A semiconductor package includes an adhesive member disposed on a package substrate to have a trapezoid cross-section view, and a semiconductor chip disposed on the adhesive member and attached to the package substrate by the adhesive member. The semiconductor chip has a first surface and a second surface facing the first surface, and the second surface of the semiconductor chip contacts the adhesive member. The semiconductor chip includes a tension supplement pattern attached to the second surface and spaced apart from the package substrate.

Abstract translation: 半导体封装包括设置在封装基板上以具有梯形横截面图的粘合构件，以及设置在粘合构件上并通过粘合构件附接到封装基板的半导体芯片。 半导体芯片具有面向第一表面的第一表面和第二表面，并且半导体芯片的第二表面接触粘合构件。 半导体芯片包括附着到第二表面并与封装衬底隔开的张力补充图案。

公开(公告)号：US20150145120A1

公开(公告)日：2015-05-28

申请号：US14245988

申请日：2014-04-04

Applicant: SK HYNIX INC.

Inventor： Dae Woong LEE

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/94 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/0557 ,  H01L2224/1148 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/14051 ,  H01L2224/14181 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/11

Abstract: A semiconductor device includes a through electrode, a pad, and a bump. The through electrode penetrates a device body of the semiconductor device. The pad is disposed over an end of the through electrode to have a first overlap region and a second overlap region that overlap with a central portion and an edge portion of the end of the through electrode, respectively. The bump is disposed over the pad to contact the second overlap region of the pad without contacting the first overlap region of the pad.

Abstract translation: 半导体器件包括贯通电极，焊盘和凸块。 穿通电极穿透半导体器件的器件本体。 焊盘设置在贯通电极的一端上，以分别具有与通孔端部的中心部分和边缘部分重叠的第一重叠区域和第二重叠区域。 凸块设置在焊盘上方以接触焊盘的第二重叠区域，而不接触焊盘的第一重叠区域。

公开(公告)号：US20190355645A1

公开(公告)日：2019-11-21

申请号：US16529548

申请日：2019-08-01

Applicant: SK hynix Inc.

Inventor： Dae Woong LEE

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/00

Abstract: A semiconductor package may include a first semiconductor chip, a second semiconductor chip, and a thermal redistribution pattern which are disposed on a package substrate. The thermal redistribution pattern may include a first end portion disposed in a high temperature region adjacent to the first semiconductor chip, a second end portion disposed in a low temperature region adjacent to the second semiconductor chip, and an extension portion connecting the first end portion to the second end portion.

公开(公告)号：US20190148257A1

公开(公告)日：2019-05-16

申请号：US16036242

申请日：2018-07-16

Applicant: SK hynix Inc.

Inventor： Dae Woong LEE

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/373 ,  H01L25/18

CPC classification number: H01L23/367 ,  H01L23/3735 ,  H01L23/3736 ,  H01L24/32 ,  H01L25/18 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/15311

Abstract: A semiconductor package may include a first semiconductor chip, a second semiconductor chip, and a thermal redistribution pattern which are disposed on a package substrate. The thermal redistribution pattern may include a first end portion disposed in a high temperature region adjacent to the first semiconductor chip, a second end portion disposed in a low temperature region adjacent to the second semiconductor chip, and an extension portion connecting the first end portion to the second end portion.

公开(公告)号：US20150270229A1

公开(公告)日：2015-09-24

申请号：US14339029

申请日：2014-07-23

Applicant: SK hynix Inc.

Inventor： Tae Min KANG ,  Dae Woong LEE ,  Jong Hoon KIM

IPC: H01L23/00 ,  H01L23/58

CPC classification number: H01L23/562 ,  H01L21/304 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/585 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/13009 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48111 ,  H01L2224/49176 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81903 ,  H01L2224/85201 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2924/00012

Abstract: A semiconductor chip includes a semiconductor substrate having a front surface, a circuit unit formed within the semiconductor substrate and extending from the front surface into the semiconductor substrate, and a rear surface opposite the front surface, and a girder beam disposed outside of the circuit unit and within the semiconductor substrate.

Abstract translation: 半导体芯片包括具有前表面的半导体衬底，形成在半导体衬底内并从前表面延伸到半导体衬底中的电路单元，以及与前表面相对的后表面，以及设置在电路单元外侧的大梁 并在半导体衬底内。