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10 条记录 (耗时 0.016 秒)

    Process for producing .alpha.-olefin polymer
    1.
    发明授权
    Process for producing .alpha.-olefin polymer 失效
    生产α-烯烃聚合物的方法

    公开(公告)号：US4315088A

    公开(公告)日：1982-02-09

    申请号：US102467

    申请日：1979-12-11

    申请人： Sadao Kitagawa ,  Isao Okada ,  Teruo Saito

    发明人： Sadao Kitagawa ,  Isao Okada ,  Teruo Saito

    IPC分类号： C08F4/00 ,  C08F4/02 ,  C08F4/44 ,  C08F4/60 ,  C08F4/64 ,  C08F10/00 ,  C08F10/04

    CPC分类号： C08F4/022 ,  C08F10/00 ,  Y10S526/906

    摘要： This invention relates to a process for producing an .alpha.-olefin polymer having a high stereoregularity in a high yield by polymerizing .alpha.-olefin in the presence of a catalyst composed of solid catalyst component (I) prepared by contacting (A) magnesium halide, (B) aromatic carboxylic acid ester, (C) halogen compound of titanium, and (D) siloxyaluminum compound with each other, and (II) an organometallic compound of a metal of Group I to III in the Periodic Table.

    摘要翻译： 本发明涉及一种通过在由（A）卤化镁（（A））和（A）制备的固体催化剂组分（I）组成的催化剂存在下聚合α-烯烃，从而以高产率制备具有高立构规整性的α-烯烃聚合物的方法， B）芳族羧酸酯，（C）钛的卤素化合物和（D）硅氧烷化合物，和（II）元素周期表中第I至III族金属的有机金属化合物。

    Process for producing olefin polymers
    2.
    发明授权
    Process for producing olefin polymers 失效
    生产烯烃聚合物的方法

    公开(公告)号：US4237254A

    公开(公告)日：1980-12-02

    申请号：US899999

    申请日：1978-04-25

    申请人： Sadao Kitagawa ,  Isao Okada ,  Teruo Saito ,  Shoichi Masukawa ,  Yoshihisa Watanabe ,  Makoto Imanari

    发明人： Sadao Kitagawa ,  Isao Okada ,  Teruo Saito ,  Shoichi Masukawa ,  Yoshihisa Watanabe ,  Makoto Imanari

    IPC分类号： C08F10/00 ,  C08F4/02 ,  C08F10/06

    CPC分类号： C08F10/00 ,  Y10S526/902 ,  Y10S526/906

    摘要： A process for producing olefin polymers comprising contacting an ethylenically unsaturated monomer comprising at least one olefin monomer with a catalyst system comprising a combination of a catalyst component I and a catalyst component II as described hereunder:Catalyst component IA solid product obtained by contacting the following constituents (a), (b) and (c) or (a), (b), (c) and (d) together:(a) A solid reaction product of a magnesium compound containing a hydroxyl group attached to magnesium and an organoaluminum compound represented by the formula R.sub.n AlX.sub.3-n wherein R represents a hydrocarbon residue having from 1 to 20 carbon atoms, X represents a halogen atom and n represents a number of greater than zero but not greater than 1.5, i.e. 0

    摘要翻译： 一种制备烯烃聚合物的方法，包括使包含至少一种烯烃单体的烯属不饱和单体与包含催化剂组分I和催化剂组分II的组合的催化剂体系接触，如下所述：催化剂组分IA固体产物通过使下列组分 （a），（b）和（c）或（a），（b），（c）和（d））：（a）含有与镁结合的羟基的镁化合物与有机铝 由式RnAlX3-n表示的化合物，其中R表示具有1至20个碳原子的烃基，X表示卤素原子，n表示大于零但不大于1.5的数，即0

    Unsaturated copolymers
    3.
    发明授权
    Unsaturated copolymers 失效
    不饱和共聚物

    公开(公告)号：US4366296A

    公开(公告)日：1982-12-28

    申请号：US339462

    申请日：1982-01-15

    申请人： Sadao Kitagawa ,  Isao Okada

    发明人： Sadao Kitagawa ,  Isao Okada

    IPC分类号： C08F2/38 ,  C08F210/02 ,  C08F210/06 ,  C08F210/18 ,  C08F210/08

    CPC分类号： C08F210/18 ,  C08F210/02 ,  C08F210/06

    摘要： A thermoplastic, substantially resinous, unsaturated, random copolymer of ethylene, propylene or 4-methyl-1-pentene with a branched 1,4-diene of the formula ##STR1## wherein R.sup.1 is an alkyl group of a maximum of 8 carbon atoms, and each of R.sup.2 and R.sup.3 is hydrogen or an alkyl of a maximum of 8 carbon atoms, exclusive of the case where both R.sup.2 and R.sup.3 are both hydrogen.

    摘要翻译： 乙烯，丙烯或4-甲基-1-戊烯与式（IMAGE）的支链1,4-二烯的热塑性基本上树脂，不饱和的无规共聚物，其中R 1是最多8个碳原子的烷基， 并且R2和R3各自为氢或最多8个碳原子的烷基，不同之处在于R2和R3均为氢的情况。

    Piezoelectric buzzer
    4.
    发明授权
    Piezoelectric buzzer 失效
    压电式蜂鸣器

    公开(公告)号：US5625248A

    公开(公告)日：1997-04-29

    申请号：US322934

    申请日：1994-10-13

    申请人： Shuho Saito ,  Isao Okada ,  Osamu Segawa ,  Toshiaki Yamashita

    发明人： Shuho Saito ,  Isao Okada ,  Osamu Segawa ,  Toshiaki Yamashita

    IPC分类号： H04R17/00 ,  G10K9/122 ,  H01L41/08

    CPC分类号： G10K9/122

    摘要： A piezoelectric buzzer includes a piezoelectric diaphragm stored in a case having a case body and a back cover, and a pair of metal terminals which are electrically connected to the piezoelectric diaphragm and drawn out from the back cover. The metal terminals have terminal drawing portions, terminal fixing portions which are arranged along an inner surface of the back cover, and connecting portions which are bent from inner ends of the terminal fixing portions so that the bent portions are substantially U-shaped as viewed from above while forward ends thereof are separated from the inner surface of the back cover and brought into contact with the piezoelectric diaphragm.

    摘要翻译： 压电蜂鸣器包括存储在具有壳体和后盖的壳体中的压电振动器和与压电振动膜电连接并从后盖引出的一对金属端子。 金属端子具有端子引出部，沿着后盖的内表面配置的端子固定部以及从端子固定部的内端弯曲的连接部，使得弯曲部从大致U字形 其前端与后盖的内表面分离，并与压电振膜接触。

    System Clock Generation Circuit
    5.
    发明申请
    System Clock Generation Circuit 审中-公开

    公开(公告)号：US20080290916A1

    公开(公告)日：2008-11-27

    申请号：US11597768

    申请日：2004-05-26

    申请人： Isao Okada ,  Tsuyoshi Hirabuki

    发明人： Isao Okada ,  Tsuyoshi Hirabuki

    IPC分类号： H03L7/06

    CPC分类号： G11B20/1403 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/1024 ,  G11B20/10425 ,  G11B20/10435 ,  G11B2020/1269 ,  G11B2220/2537 ,  H03L7/093 ,  H03L7/23

    摘要： A system clock signal generator circuit comprising a first PLL circuit that is frequency and phase locked to a wobble signal; a frequency and phase comparator for comprising a first output signal from the first PLL circuit with a system clock signal as frequency divided by M and for outputting a second output signal based on the differences in frequency and in phase; a PLL filter for providing a predetermined cutoff to the second output signal to output a third output signal; a pulse width modulating circuit for generating a pulse wave, the carrier frequency of which is a second reference clock signal, and for outputting a fourth output signal obtained by modulating the pulse width of the pulse wave by the third output signal; a low pass filter for smoothing the fourth output signal to output a fifth output signal; a VCO circuit the control voltage of which is the fifth output signal; a first frequency divider circuit for frequency dividing an output signal of the VCO circuit by N to output a system clock signal; and a second frequency divider circuit for frequency dividing, by M, and feeding the system clock signal back to the frequency and phase comparator.

    Demodulation circuit, a decode circuit and a digital PLL circuit for an optical disc apparatus
    6.
    发明授权
    Demodulation circuit, a decode circuit and a digital PLL circuit for an optical disc apparatus 有权
    解调电路，解码电路和用于光盘装置的数字PLL电路

    公开(公告)号：US06359949B1

    公开(公告)日：2002-03-19

    申请号：US09620054

    申请日：2000-07-20

    申请人： Isao Okada ,  Tsuyoshi Hirabuki

    发明人： Isao Okada ,  Tsuyoshi Hirabuki

    IPC分类号： H04L2300

    CPC分类号： G11B27/24 ,  G11B20/10009 ,  G11B20/1419 ,  G11B20/18 ,  G11B27/3027 ,  G11B2220/218 ,  G11B2220/2545 ,  H03M5/12

    摘要： An optical disc apparatus has a demodulation circuit performing an FSK demodulation by being provided with a binary signal which is obtained by binarizing a signal reproduced from an optical disc on which an FSK modulation signal is previously recorded. An edge interval of the binary signal is measured. An FSK modulation component is obtained from a difference between a measured edge interval value and a previously determined edge interval reference value. A demodulation value is obtained based on a moving average of the FSK modulation component. A moving average of the demodulation value is compared with a reference value so as to obtain a binary FSK demodulation signal. Additionally, the optical disc apparatus includes a decode circuit for decoding binary data from a biphase code signal which is reproduced from an optical disc and to be inverted at an end of each bit. When an inversion of the biphase code signal is not performed at an end of a bit, the decode circuit corrects the binary data immediately before or after the end of the bit. Further, the optical disc apparatus includes a digital PLL circuit which divides a frequency of a demodulated signal reproduced from the optical disc by a predetermined dividing ratio. A clock signal is obtained based on an edge interval value of the divided modulated signal.

    摘要翻译： 光盘装置具有通过提供二进制信号来执行FSK解调的解调电路，二进制信号是通过二值化从先前记录有FSK调制信号的光盘再现的信号而获得的。 测量二进制信号的边沿间隔。 从测量的边缘间隔值和预先确定的边缘间隔参考值之间的差获得FSK调制分量。 基于FSK调制分量的移动平均值获得解调值。 将解调值的移动平均值与参考值进行比较，以获得二进制FSK解调信号。 此外，光盘装置包括一个解码电路，用于从一个从光盘再现的双相码信号中解码二进制数据，并在每个位的末尾被反相。 当在比特结束时不执行双相码信号的反转时，解码电路在比特结束之前或之后立即校正二进制数据。 此外，光盘装置包括数字PLL电路，其将从光盘再现的解调信号的频率除以预定的分频比。 基于分频调制信号的边沿间隔值获得时钟信号。

    Demodulation circuit, a decode circuit and a digital PLL circuit for an optical disc apparatus
    7.
    发明授权
    Demodulation circuit, a decode circuit and a digital PLL circuit for an optical disc apparatus 失效
    解调电路，解码电路和用于光盘装置的数字PLL电路

    公开(公告)号：US06175542B1

    公开(公告)日：2001-01-16

    申请号：US09084359

    申请日：1998-05-22

    申请人： Isao Okada ,  Tsuyoshi Hirabuki

    发明人： Isao Okada ,  Tsuyoshi Hirabuki

    IPC分类号： G11B7005

    CPC分类号： G11B27/24 ,  G11B20/10009 ,  G11B20/1419 ,  G11B20/18 ,  G11B27/3027 ,  G11B2220/218 ,  G11B2220/2545 ,  H03M5/12

    摘要： An optical disc apparatus has a demodulation circuit performing an FSK demodulation by being provided with a binary signal which is obtained by binarizing a signal reproduced from an optical disc on which an FSK modulation signal is previously recorded. An edge interval of the binary signal is measured. An FSK modulation component is obtained from a difference between a measured edge interval value and a previously determined edge interval reference value. A demodulation value is obtained based on a moving average of the FSK modulation component. A moving average of the demodulation value is compared with a reference value so as to obtain a binary FSK demodulation signal. Additionally, the optical disc apparatus includes a decode circuit for decoding binary data from a biphase code signal which is reproduced from an optical disc and to be inverted at an end of each bit. When an inversion of the biphase code signal is not performed at an end of a bit, the decode circuit corrects the binary data immediately before or after the end of the bit. Further, the optical disc apparatus includes a digital PLL circuit which divides a frequency of a demodulated signal reproduced from the optical disc by a predetermined dividing ratio. A clock signal is obtained based on an edge interval value of the divided modulated signal.

    摘要翻译： 光盘装置具有通过提供二进制信号来执行FSK解调的解调电路，二进制信号是通过二值化从先前记录有FSK调制信号的光盘再现的信号而获得的。 测量二进制信号的边沿间隔。 从测量的边缘间隔值和预先确定的边缘间隔参考值之间的差获得FSK调制分量。 基于FSK调制分量的移动平均值获得解调值。 将解调值的移动平均值与参考值进行比较，以获得二进制FSK解调信号。 此外，光盘装置包括一个解码电路，用于从一个从光盘再现的双相码信号中解码二进制数据，并在每个位的末尾被反相。 当在比特结束时不执行双相码信号的反转时，解码电路在比特结束之前或之后立即校正二进制数据。 此外，光盘装置包括数字PLL电路，其将从光盘再现的解调信号的频率除以预定的分频比。 基于分频调制信号的边沿间隔值获得时钟信号。

    Servo circuit, digital PLL circuit and optical disk device
    9.
    发明授权
    Servo circuit, digital PLL circuit and optical disk device 失效
    伺服电路，数字PLL电路和光盘设备

    公开(公告)号：US5946279A

    公开(公告)日：1999-08-31

    申请号：US839015

    申请日：1997-04-23

    申请人： Isao Okada ,  Tsuyoshi Hirabuki

    发明人： Isao Okada ,  Tsuyoshi Hirabuki

    IPC分类号： G11B19/247 ,  G11B19/26 ,  G11B19/28 ,  G11B20/10 ,  G11B20/14 ,  G11B27/19 ,  G11B27/24 ,  G11B27/30 ,  H03L7/08 ,  H03L7/085 ,  H03L7/181 ,  G11B7/00

    CPC分类号： H03L7/181 ,  G11B19/247 ,  G11B19/26 ,  G11B19/28 ,  G11B20/10 ,  G11B20/1025 ,  G11B20/1403 ,  G11B27/24 ,  H03L7/08 ,  H03L7/085 ,  E05Y2400/30 ,  G11B2220/218 ,  G11B2220/2545 ,  G11B27/3027 ,  H03L2207/50

    摘要： A speed error detecting portion detects a speed error which is a frequency difference between a reproduced clock signal which is reproduced from a recording medium and a reference clock signal. A first phase error detecting portion detects a phase error which is a phase difference between the reproduced clock signal and the reference clock signal. A servo signal generating portion generates a servo signal which is used for eliminating the speed error and phase error. A second phase error detecting portion detects a phase error which is a phase difference between a reproduced synchronization signal reproduced from the recording medium separately from the reproduced clock signal and a reference synchronization signal. A reference phase changing portion changes the phase of the reference clock signal based on the phase error detected by the second phase error detecting portion. A reference frequency changing portion changes the frequency of the reference clock signal based on the phase error detected by the second phase error detecting portion.

    摘要翻译： 速度误差检测部分检测作为从记录介质再现的再生时钟信号与基准时钟信号之间的频率差的速度误差。 第一相位误差检测部分检测作为再现的时钟信号和参考时钟信号之间的相位差的相位误差。 伺服信号产生部分产生用于消除速度误差和相位误差的伺服信号。 第二相位误差检测部分检测作为从再现的时钟信号分离的从记录介质再现的再现的同步信号与基准同步信号之间的相位差的相位误差。 参考相位改变部分基于由第二相位误差检测部分检测到的相位误差来改变参考时钟信号的相位。 参考频率改变部分基于由第二相位误差检测部分检测到的相位误差来改变参考时钟信号的频率。