公开(公告)号：US11257723B2

公开(公告)日：2022-02-22

申请号：US16698160

申请日：2019-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Do-Hyun Kim ,  Sunwon Kang ,  Hogeon Song ,  Kyung Suk Oh

IPC: H01L23/544 ,  H01L21/18 ,  H01L21/304 ,  H01L21/66 ,  H01L21/67

Abstract: An inspection system for a semiconductor package includes an inspection apparatus that includes a stage on which the semiconductor package is loaded, and a computer coupled to the inspection apparatus. The semiconductor package may include a first semiconductor chip and a second semiconductor chip on the first semiconductor chip, the computer may provide first identification information about the first semiconductor chip and second identification information about the second semiconductor chip, and the computer may control the inspection apparatus to selectively perform a package test process on one of the first and second semiconductor chips, the one of the first and second semiconductor chips being identified as a good chip based on the first identification information and the second identification information.

公开(公告)号：US10008488B2

公开(公告)日：2018-06-26

申请号：US15489031

申请日：2017-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongkwan Lee ,  Kundae Yeom ,  Jongho Lee ,  Hogeon Song

IPC: H01L25/18 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L25/18 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16141 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4911 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00012

Abstract: In one embodiment, the semiconductor module includes a module substrate and a first substrate mounted on and electrically connected to a first surface of the module substrate. The first substrate has one or more first electrical connectors of the semiconductor module, and the first substrate electrically connecting the first electrical connector to the module substrate.

公开(公告)号：US09202716B2

公开(公告)日：2015-12-01

申请号：US13626012

申请日：2012-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Woo Park ,  Hogeon Song ,  Seokhyun Lee

IPC: H01L23/34 ,  H01L21/56 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L23/13 ,  H01L23/12 ,  H01L23/057 ,  H01L23/055 ,  H01L23/24 ,  H01L23/053 ,  H01L23/02 ,  H01L23/04 ,  H01L23/495 ,  H01L23/08 ,  H01L23/492 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L23/02 ,  H01L23/04 ,  H01L23/053 ,  H01L23/055 ,  H01L23/057 ,  H01L23/08 ,  H01L23/12 ,  H01L23/13 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/4926 ,  H01L23/49575 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/24011 ,  H01L2224/24146 ,  H01L2224/32145 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/82101 ,  H01L2224/96 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/82 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A fan-out wafer level package may include at least two semiconductor chips; an insulating layer covering portions of a first semiconductor chip; a mold layer covering portions of a second semiconductor chip; a redistribution line pattern in the insulating layer; and/or an external terminal on the insulating layer. The first semiconductor chip may be stacked relative to the second semiconductor chip. The redistribution line pattern may be electrically connected to the at least two semiconductor chips. The external terminal may be electrically connected to the redistribution line pattern. A fan-out wafer level package may include at least three semiconductor chips; an insulating layer covering portions of first semiconductor chips; a mold layer covering portions of a second semiconductor chip; a redistribution line pattern in the insulating layer; and/or an external terminal on the insulating layer. The first semiconductor chips may be stacked relative to the second semiconductor chip.

Abstract translation: 扇出晶片级封装可以包括至少两个半导体芯片; 覆盖第一半导体芯片的部分的绝缘层; 覆盖第二半导体芯片的部分的模具层; 绝缘层中的再分布线图案; 和/或绝缘层上的外部端子。 第一半导体芯片可以相对于第二半导体芯片堆叠。 再分布线图案可以电连接到至少两个半导体芯片。 外部端子可以电连接到再分配线图案。 扇出晶片级封装可以包括至少三个半导体芯片; 覆盖第一半导体芯片的部分的绝缘层; 覆盖第二半导体芯片的部分的模具层; 绝缘层中的再分布线图案; 和/或绝缘层上的外部端子。 第一半导体芯片可以相对于第二半导体芯片堆叠。

公开(公告)号：US20140312505A1

公开(公告)日：2014-10-23

申请号：US14319688

申请日：2014-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： SeYoung Jeong ,  Sunpil Youn ,  Hogeon Song

IPC: H01L23/48 ,  H01L27/108

CPC classification number: H01L23/481 ,  H01L24/81 ,  H01L25/0657 ,  H01L27/108 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  Y10T428/12708 ,  H01L2924/00

Abstract: A semiconductor device includes a first semiconductor chip, a first connection structure disposed on a first side of the first semiconductor chip, a second semiconductor chip disposed on a second side of the first semiconductor chip, and a second connection structure disposed between the first and second semiconductor chips, wherein a number of the second connection structures is less than a number of the first connection structures.

Abstract translation: 半导体器件包括第一半导体芯片，设置在第一半导体芯片的第一侧上的第一连接结构，设置在第一半导体芯片的第二侧上的第二半导体芯片，以及设置在第一和第二半导体芯片之间的第二连接结构 半导体芯片，其中多个第二连接结构小于第一连接结构的数量。