公开(公告)号：US20240040797A1

公开(公告)日：2024-02-01

申请号：US18142291

申请日：2023-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunmook CHOI ,  Jihong KIM ,  Siyeon CHO

IPC: H10B51/30

CPC classification number: H10B51/30

Abstract: A three-dimensional non-volatile memory device includes horizontal word lines separated from each other in a vertical direction, horizontal ferroelectric layers arranged among the horizontal word lines, the horizontal ferroelectric layers including upper horizontal ferroelectric layers and lower horizontal ferroelectric layers, vertical ferroelectric layers contacting side walls of the horizontal ferroelectric layers and extending in the vertical direction, a semiconductor pillar passing through the horizontal word lines in the vertical direction, and a channel region between the horizontal word lines and the semiconductor pillar, wherein the upper horizontal ferroelectric layers and the lower horizontal ferroelectric layers are separated from each other by an air gap in the vertical direction.

公开(公告)号：US20230169999A1

公开(公告)日：2023-06-01

申请号：US17895642

申请日：2022-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minho KIM ,  Hyunmook CHOI

IPC: G11C7/10 ,  G11C29/52 ,  G06F7/544

CPC classification number: G11C7/1039 ,  G11C29/52 ,  G06F7/5443

Abstract: A nonvolatile memory device includes a memory cell region and a peripheral circuit region disposed below the memory cell region. The peripheral circuits include a page buffer, a row decoder, and other peripheral circuits, wherein the page buffer is included in a page buffer block disposed on a lower surface of the first semiconductor substrate to be distinguished from other circuits included in the peripheral circuit region in a first direction perpendicular to an upper surface of the first semiconductor substrate, is connected to the memory cell region through a connection portion penetrating through the first semiconductor substrate, and includes a plurality of vertical transistors each defined by a source region, a channel region, and a drain region stacked in sequence in the first direction.

公开(公告)号：US20240179913A1

公开(公告)日：2024-05-30

申请号：US18489224

申请日：2023-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunmook CHOI ,  Jihong KIM ,  Hyunmog PARK

IPC: H10B43/27 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506 ,  H01L2225/0651

Abstract: A semiconductor device including first gate electrodes stacked on a substrate and spaced apart from each other, a first channel structure passing through the first gate electrodes, the first channel structure including a first channel layer, a first dielectric layer between the first channel layer and the first gate electrodes, a first buried insulating layer filling an interior of the first channel layer, an auxiliary channel layer covering at least a portion of the first channel layer and the first dielectric layer, and a first channel pad on the first buried insulating layer, and isolation regions passing through the first gate electrodes, the isolation regions and spaced apart from each other may be provided. The auxiliary channel layer may be in contact with the first channel pad. The first channel pad may be spaced apart from the first dielectric layer by the auxiliary channel layer.

公开(公告)号：US20230284449A1

公开(公告)日：2023-09-07

申请号：US18058014

申请日：2022-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunmook CHOI

IPC: H01L29/76 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L27/11524 ,  H01L23/5283 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

Abstract: A semiconductor device may include a lower interconnection structure electrically connected to circuit devices on a first substrate, a lower bonding structure connected to the lower interconnection structure and an upper bonding structure, an upper interconnection structure connected to the upper bonding structure, a second substrate on the upper interconnection structure, gate electrodes between the upper interconnection structure and the second substrate, channel structures penetrating through the gate electrodes. The gate electrodes may be spaced apart from each other in a vertical direction. The gate electrodes may include first and second gate electrodes. Each of the channel structures may include a channel layer, which may include a first semiconductor material layer adjacent to the first gate electrodes and a second semiconductor material layer adjacent to the second gate electrodes. Each of the first and second semiconductor material layers may have a single crystal structure or a single crystal-like structure.

公开(公告)号：US20240397723A1

公开(公告)日：2024-11-28

申请号：US18661906

申请日：2024-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunmook CHOI

IPC: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B51/20 ,  H10B51/30 ,  H10B63/00

Abstract: An integrated circuit device includes a semiconductor substrate, a gate stack including a plurality of gate layers and a plurality of insulating layers that are alternately stacked on the semiconductor substrate, a plurality of channel structures extending to pass through the gate stack in a vertical direction, a word line cut extending to pass through the gate stack in the vertical direction, a string selection line stack on the gate stack, and a plurality of gate structures extending to pass the string selection line stack in the vertical direction, the plurality of gate structures completely overlapping the plurality of channel structures corresponding thereto, wherein an inter-gate cutting film is between two adjacent gate structures, which are adjacent to each other in an oblique direction, from among the plurality of gate structures, and the two adjacent gate structures are symmetrically positioned in a mirror-image relationship about the inter-gate cutting film.

公开(公告)号：US20230171964A1

公开(公告)日：2023-06-01

申请号：US17898682

申请日：2022-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minho KIM ,  Hyunmook CHOI

IPC: H01L27/11573 ,  G11C16/04 ,  H01L27/11529 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11524 ,  G11C16/08

CPC classification number: H01L27/11573 ,  G11C16/08 ,  G11C16/0483 ,  H01L23/5283 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11529

Abstract: A nonvolatile memory device including a first semiconductor structure including a first semiconductor substrate, a memory cell area including a plurality of memory cells disposed on the first semiconductor substrate, and a first metal pad disposed on the memory cell area; a second semiconductor structure including a second semiconductor substrate, a page buffer disposed on the second semiconductor substrate, and a second metal pad bonded to the first metal pad; and a third semiconductor structure including a third semiconductor substrate, a buffer memory and peripheral circuits disposed on the third semiconductor substrate, and a third metal pad connected to the peripheral circuits, wherein the page buffer includes a plurality of vertical transistors including a source area, a channel area, and a drain area sequentially stacked in a first direction, and the first semiconductor structure to third semiconductor structure are connected in the first direction.

公开(公告)号：US20230180475A1

公开(公告)日：2023-06-08

申请号：US17894524

申请日：2022-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunmook CHOI ,  Jihong KIM ,  Kyoungcho NA

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  G11C16/14

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  G11C16/14

Abstract: A method for manufacturing a semiconductor device including forming a first substrate and a second substrate thereon; forming a first stack region by alternately stacking first interlayer insulating and sacrificial layers on the second substrate; forming a second stack region by alternately stacking second interlayer insulating and sacrificial layers on the first stack region; forming first openings spaced apart from each other in the first direction by partially removing the second stack region; forming a first filling insulating layer in the first openings; forming a second opening by partially removing the second stack region between the first openings; removing the second sacrificial layers exposed through the second opening; forming a lower separation region including the first filling insulating layer and a second filling insulating layer, by forming the second filling insulating layer in the second opening and regions in which the second sacrificial layers have been removed.

公开(公告)号：US20230169937A1

公开(公告)日：2023-06-01

申请号：US18103619

申请日：2023-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunmook CHOI

IPC: G09G5/22

CPC classification number: G09G5/227 ,  G09G2310/08 ,  G09G2340/0414 ,  G09G2340/0435 ,  G09G2354/00

Abstract: A method of controlling a display device may comprise: identifying a first area among all areas of a content displayable on a display; and scanning multiple pixel lines by multiple pixel lines in the first area and scanning one pixel line by one pixel line in a second area among all the areas of content which remain after excluding the first area, wherein at least one of a size and a position of the first area and a number of first areas is variable.

公开(公告)号：US20230077589A1

公开(公告)日：2023-03-16

申请号：US17679863

申请日：2022-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunmook CHOI ,  Jooheon KANG ,  Sanghoon KIM ,  Jihong KIM

IPC: H01L27/24

Abstract: A semiconductor device includes a horizontal wiring layer on a substrate, a stack structure disposed on the horizontal wiring layer and including insulating layers and electrode layers alternately stacked on each other, and a pillar structure extending into the horizontal wiring layer and extending through the stack structure. The electrode layers include one or a plurality of selection lines adjacent to an uppermost end of the stack structure, and word lines surrounding the stack structure below the one or plurality of selection lines. The pillar structure includes a variable resistive layer, a channel layer between the variable resistive layer and the stack structure, a gate dielectric layer between the channel layer and the stack structure, and a blocking pattern disposed between the variable resistive layer and the channel layer and being adjacent to a first selection line among the one or plurality of selection lines.