公开(公告)号：US10067584B2

公开(公告)日：2018-09-04

申请号：US14838710

申请日：2015-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inkyeong Yoo ,  Jungwoo Kim ,  Byeonghak Kang ,  Kwonyoung Kim ,  Jongwan Kim

IPC: G06F3/041 ,  G02B1/00 ,  G02B1/14 ,  G02B5/20 ,  G02B5/26

Abstract: A film for writing may include: a rough layer, including a non-flat surface, configured to transmit a first light beam and a second light beam of different wavelength bands; and/or a photonic crystal layer, arranged on the rough layer, configured to transmit the first light beam and configured to reflect the second light beam. A film for writing, which transmits visible rays, may include: a non-flat layer. A difference between a maximum thickness and a minimum thickness of the non-flat layer may be from about 220 nanometers (nm) to about 2 microns (μm). A film for writing may include: a first layer; and/or a second layer on the first layer. The first layer may be configured to transmit first and second light beams of different frequency bands. The second layer may be configured to transmit the first light beam, but to reflect the second light beam.

公开(公告)号：US09767407B2

公开(公告)日：2017-09-19

申请号：US15267600

申请日：2016-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongho Cho ,  Inkyeong Yoo ,  Hojung Kim

IPC: G11C16/10 ,  G06N3/04 ,  H01L29/792 ,  H01L29/423 ,  H01L29/788 ,  H01L29/10 ,  G11C16/04 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C11/54 ,  G11C11/56 ,  G11C13/00

CPC classification number: G06N3/04 ,  G11C11/54 ,  G11C11/56 ,  G11C13/0002 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C2213/72 ,  G11C2213/79 ,  H01L29/1083 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/7881 ,  H01L29/792

Abstract: Provided are a weighting device that may be driven at a low voltage and is capable of embodying multi-level weights, a neural network, and a method of operating the weighting device. The weighting device includes a switching layer that may switch between a high resistance state and a low resistance state based on a voltage applied thereto and a charge trap material layer that traps or discharges charges according to a resistance state of the switching layer. The weighting device may be used for controlling a weight in a neural network.

公开(公告)号：US09773802B2

公开(公告)日：2017-09-26

申请号：US15209371

申请日：2016-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Xianyu Wenxu ,  Inkyeong Yoo ,  Hojung Kim ,  Seong ho Cho

IPC: H01L29/792 ,  H01L27/1157 ,  H01L21/28 ,  H01L21/02 ,  H01L21/762 ,  H01L21/308 ,  H01L29/08 ,  H01L29/06 ,  G11C11/54 ,  H01L29/68 ,  H01L45/00 ,  H01L29/66 ,  H01L27/105

CPC classification number: H01L27/1157 ,  G11C11/54 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/53 ,  G11C2213/79 ,  H01L21/0217 ,  H01L21/02175 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/762 ,  H01L21/76202 ,  H01L21/76224 ,  H01L27/1052 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66833 ,  H01L29/685 ,  H01L45/00

Abstract: Example embodiments relate to a method of fabricating a synapse memory device capable of being driven at a low voltage and realizing a multi-level memory. The synapse memory device includes a two-transistor structure in which a drain region of a first transistor including a memory layer and a first source region of a second transistor share a source-drain shared area. The synapse memory device is controlled by applying a voltage through the source-drain shared area. The memory layer includes a charge trap layer and a threshold switching layer, and may realize a non-volatile multi-level memory function.

公开(公告)号：US09747985B2

公开(公告)日：2017-08-29

申请号：US15206791

申请日：2016-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inkyeong Yoo ,  Hojung Kim ,  Seongho Cho

IPC: G11C16/04 ,  H01L27/11568 ,  H01L23/528 ,  H01L45/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/14

CPC classification number: G11C16/0466 ,  G11C16/0433 ,  G11C16/045 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L21/28273 ,  H01L23/528 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324

Abstract: A non-volatile inverter may be configured to perform a memory function. The non-volatile inverter may include first and second transistors. The first transistor may include a first gate electrode, a first electrode, and a second electrode. The second transistor may include a second gate electrode and a third electrode and may share the second electrode with the first transistor. The first transistor may include a first switching layer and a charge trap layer. The first switching layer may be configured to switch between a high resistance state and a low resistance state. The charge trap layer may be configured to trap or de-trap charges according to the resistance state of the first switching layer. The first switching layer may include a P-N diode. The second transistor may include a second gate switching layer and a charge trap layer.