公开(公告)号：US11283235B2

公开(公告)日：2022-03-22

申请号：US16538044

申请日：2019-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pil-Kyu Kang ,  Seok-Ho Kim ,  Tae-Yeong Kim ,  Hoe-Chul Kim ,  Hoon-Joo Na

IPC: H01S5/0236 ,  H01S5/02 ,  H01S5/323 ,  H01S5/02251

Abstract: A semiconductor laser device may include a first cladding on a substrate, an optical waveguide on the first cladding, a laser light source chip on the optical waveguide to generate a laser beam, a first adhesive layer between the optical waveguide and the laser light source chip, and a second adhesive layer covering a sidewall of the laser light source chip.

公开(公告)号：US09520361B2

公开(公告)日：2016-12-13

申请号：US14937406

申请日：2015-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pil-Kyu Kang ,  Seok-Ho Kim ,  Tae-Yeong Kim ,  Hyo-Ju Kim ,  Byung-Lyul Park ,  Joo-Hee Jang ,  Jin-Ho Chun

IPC: H01L23/532 ,  H01L25/065

CPC classification number: H01L23/53228 ,  H01L21/76843 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L25/0657 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/08121 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate, a first conductive structure on the substrate, and a second conductive structure on the first conductive structure. The semiconductor device includes first and second metal-diffusion-blocking layers on respective sidewalls of the first and second conductive structures. The semiconductor device includes an insulating layer between the first and second metal-diffusion-blocking layers. Moreover, the semiconductor device includes a metal-diffusion-shield pattern in the insulating layer and spaced apart from the first conductive structure.

Abstract translation: 提供半导体器件。 半导体器件包括衬底，衬底上的第一导电结构和第一导电结构上的第二导电结构。 半导体器件包括在第一和第二导电结构的相应侧壁上的第一和第二金属扩散阻挡层。 半导体器件包括在第一和第二金属扩散阻挡层之间的绝缘层。 此外，半导体器件在绝缘层中包括金属扩散屏蔽图案并且与第一导电结构间隔开。

公开(公告)号：US20160141249A1

公开(公告)日：2016-05-19

申请号：US14937406

申请日：2015-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pil-Kyu Kang ,  Seok-Ho Kim ,  Tae-Yeong Kim ,  Hyo-Ju Kim ,  Byung-Lyul Park ,  Joo-Hee Jang ,  Jin-Ho Chun

IPC: H01L23/532 ,  H01L25/065

CPC classification number: H01L23/53228 ,  H01L21/76843 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L25/0657 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/08121 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate, a first conductive structure on the substrate, and a second conductive structure on the first conductive structure. The semiconductor device includes first and second metal-diffusion-blocking layers on respective sidewalls of the first and second conductive structures. The semiconductor device includes an insulating layer between the first and second metal-diffusion-blocking layers. Moreover, the semiconductor device includes a metal-diffusion-shield pattern in the insulating layer and spaced apart from the first conductive structure.

Abstract translation: 提供半导体器件。 半导体器件包括衬底，衬底上的第一导电结构和第一导电结构上的第二导电结构。 半导体器件包括在第一和第二导电结构的相应侧壁上的第一和第二金属扩散阻挡层。 半导体器件包括在第一和第二金属扩散阻挡层之间的绝缘层。 此外，半导体器件在绝缘层中包括金属扩散屏蔽图案并且与第一导电结构间隔开。

公开(公告)号：US09865581B2

公开(公告)日：2018-01-09

申请号：US14940621

申请日：2015-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo-Hee Jang ,  Pil-Kyu Kang ,  Seok-Ho Kim ,  Tae-Yeong Kim ,  Hyo-Ju Kim ,  Byung-Lyul Park ,  Jum-Yong Park ,  Jin-Ho An ,  Kyu-Ha Lee ,  Yi-Koan Hong

IPC: H01L25/00 ,  H01L23/532 ,  H01L21/768 ,  H01L27/146

CPC classification number: H01L25/50 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/1469 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08121 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/04941 ,  H01L2924/04953

Abstract: A first insulating layer is formed on a substrate. An opening is formed in the first insulating layer. A barrier layer is formed on the first insulating layer and conforming to sidewalls of the first insulating layer in the opening, and a conductive layer is formed on the barrier layer. Chemical mechanical polishing is performed to expose the first insulating layer and leave a barrier layer pattern in the opening and a conductive layer pattern on the barrier layer pattern in the opening, wherein a portion of the conductive layer pattern protrudes above an upper surface of the insulating layer and an upper surface of the barrier layer pattern. A second insulating layer is formed on the first insulating layer, the barrier layer pattern and the conductive layer pattern and planarized to expose the conductive layer pattern. A second substrate may be bonded to the exposed conductive layer pattern.

公开(公告)号：US10763243B2

公开(公告)日：2020-09-01

申请号：US16135122

申请日：2018-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Hyung Kim ,  Sung-Hyup Kim ,  Kyeong-Bin Lim ,  Seok-Ho Kim ,  Tae-Yeong Kim

IPC: H01L25/065 ,  H01L21/67 ,  H01L25/00 ,  H01L21/66 ,  H01L21/687 ,  H01L21/68

Abstract: A substrate bonding apparatus and a method of bonding substrates, the apparatus including an upper chuck securing a first substrate onto a lower surface thereof such that the first substrate is downwardly deformed into a concave surface profile; a lower chuck arranged under the upper chuck and securing a second substrate onto an upper surface thereof such that the second substrate is upwardly deformed into a convex surface profile; and a chuck controller controlling the upper chuck and the lower chuck to secure the first substrate and the second substrate, respectively, and generating a shape parameter for changing a shape of the second substrate to the convex surface profile from a flat surface profile.

公开(公告)号：US20160141282A1

公开(公告)日：2016-05-19

申请号：US14940621

申请日：2015-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo-Hee Jang ,  Pil-Kyu Kang ,  Seok-Ho Kim ,  Tae-Yeong Kim ,  Hyo-Ju Kim ,  Byung-Lyul Park ,  Jum-Yong Park ,  Jin-Ho An ,  Kyu-Ha Lee ,  Yi-Koan Hong

IPC: H01L25/00 ,  H01L21/321

CPC classification number: H01L25/50 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/1469 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08121 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/04941 ,  H01L2924/04953

Abstract: A first insulating layer is formed on a substrate. An opening is formed in the first insulating layer. A barrier layer is formed on the first insulating layer and conforming to sidewalls of the first insulating layer in the opening, and a conductive layer is formed on the barrier layer. Chemical mechanical polishing is performed to expose the first insulating layer and leave a barrier layer pattern in the opening and a conductive layer pattern on the barrier layer pattern in the opening, wherein a portion of the conductive layer pattern protrudes above an upper surface of the insulating layer and an upper surface of the barrier layer pattern. A second insulating layer is formed on the first insulating layer, the barrier layer pattern and the conductive layer pattern and planarized to expose the conductive layer pattern. A second substrate may be bonded to the exposed conductive layer pattern.

Abstract translation: 在基板上形成第一绝缘层。 在第一绝缘层中形成开口。 阻挡层形成在第一绝缘层上并与开口中的第一绝缘层的侧壁一致，并且在阻挡层上形成导电层。 执行化学机械抛光以露出第一绝缘层并在开口中留下阻挡层图案，并且在开口中的阻挡层图案上具有导电层图案，其中导电层图案的一部分突出于绝缘体的上表面上方 层和阻挡层图案的上表面。 在第一绝缘层，阻挡层图案和导电层图案上形成第二绝缘层，并平坦化以暴露导电层图案。 第二衬底可以结合到暴露的导电层图案。

公开(公告)号：US09287251B2

公开(公告)日：2016-03-15

申请号：US14794561

申请日：2015-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pil-Kyu Kang ,  Seok-Ho Kim ,  Tae-Yeong Kim ,  Hyo-Ju Kim ,  Byung-Lyul Park ,  Yeun-Sang Park ,  Jin-Ho An ,  Ho-Jin Lee ,  Joo-Hee Jang ,  Deok-Young Jung

IPC: H01L21/00 ,  H01L25/00 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/76831 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08121 ,  H01L2224/08147 ,  H01L2224/80013 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/00014 ,  H01L2924/049 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/00012

Abstract: In a method, a first opening is formed in a first insulating interlayer on a first substrate. A first conductive pattern structure contacting a first diffusion prevention insulation pattern and having a planarized top surface is formed in the first opening. Likewise, a second conductive pattern structure contacting a second diffusion prevention insulation pattern is formed in a second insulating interlayer on a second substrate. A plasma treatment process is performed on at least one of the first and second substrates having the first and second conductive pattern structures thereon, respectively. The first and second conductive pattern structures are contacted to each other to bond the first and second substrates.

Abstract translation: 在一种方法中，第一开口形成在第一基板上的第一绝缘中间层中。 在第一开口中形成有与第一扩散防止绝缘图案接触并具有平坦化顶表面的第一导电图案结构。 类似地，在第二基板上的第二绝缘中间层中形成接触第二扩散防止绝缘图案的第二导电图案结构。 在其上分别具有第一和第二导电图案结构的第一和第二基板中的至少一个上执行等离子体处理工艺。 第一和第二导电图案结构彼此接触以接合第一和第二基板。

公开(公告)号：US20160020197A1

公开(公告)日：2016-01-21

申请号：US14794561

申请日：2015-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pil-Kyu Kang ,  Seok-Ho Kim ,  Tae-Yeong Kim ,  Hyo-Ju Kim ,  Byung-Lyul Park ,  Yeun-Sang Park ,  Jin-Ho An ,  Ho-Jin Lee ,  Joo-Hee Jang ,  Deok-Young Jung

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L25/50 ,  H01L21/76831 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08121 ,  H01L2224/08147 ,  H01L2224/80013 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/00014 ,  H01L2924/049 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/00012

Abstract: In a method, a first opening is formed in a first insulating interlayer on a first substrate. A first conductive pattern structure contacting a first diffusion prevention insulation pattern and having a planarized top surface is formed in the first opening. Likewise, a second conductive pattern structure contacting a second diffusion prevention insulation pattern is formed in a second insulating interlayer on a second substrate, plasma treatment process is performed on at least one of the first and second substrates having the first and second conductive pattern structures thereon, respectively. The first and second conductive pattern structures are contacted to each other to bond the first and second substrates.

Abstract translation: 在一种方法中，第一开口形成在第一基板上的第一绝缘中间层中。 在第一开口中形成有与第一扩散防止绝缘图案接触并具有平坦化顶表面的第一导电图案结构。 类似地，在第二基板上的第二绝缘中间层中形成接触第二扩散防止绝缘图案的第二导电图案结构，在其上具有第一和第二导电图案结构的第一和第二基板中的至少一个上执行等离子体处理工艺， ， 分别。 第一和第二导电图案结构彼此接触以接合第一和第二基板。