公开(公告)号：US11283235B2

公开(公告)日：2022-03-22

申请号：US16538044

申请日：2019-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pil-Kyu Kang ,  Seok-Ho Kim ,  Tae-Yeong Kim ,  Hoe-Chul Kim ,  Hoon-Joo Na

IPC: H01S5/0236 ,  H01S5/02 ,  H01S5/323 ,  H01S5/02251

Abstract: A semiconductor laser device may include a first cladding on a substrate, an optical waveguide on the first cladding, a laser light source chip on the optical waveguide to generate a laser beam, a first adhesive layer between the optical waveguide and the laser light source chip, and a second adhesive layer covering a sidewall of the laser light source chip.

公开(公告)号：US10523302B2

公开(公告)日：2019-12-31

申请号：US15763002

申请日：2016-09-23

Applicant: Samsung Electronics Co., Ltd ,  Korea University Research and Business Foundation

Inventor： Inkyu Lee ,  Jong-Ho Oh ,  Bong-Jin Kim ,  Tae-Yeong Kim ,  Min-Ki Ahn ,  Tae-Seok Oh ,  Seok-Ju Jang

IPC: H04B7/06 ,  H04B7/04 ,  H04B7/08 ,  H04B7/0491

Abstract: The present invention relates to a 5th-generation (5G) or pre-5G communication system which is provided for supporting a higher data transfer rate after a 4th-generation (4G) communication system such as a long term evolution (LTE). The present invention provides a method for selecting, by an access point (AP), a beam in a communication system supporting a beamforming scheme, the method comprising: a step of transmitting information which indicates whether or not a duplicated beacon transmission interval (BTI) is operated; and a step of performing a transmit sector sweep (TXSS) process at least twice during the duplicated BTI.

公开(公告)号：US20140199810A1

公开(公告)日：2014-07-17

申请号：US14153545

申请日：2014-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Ho Park ,  Pil-Kyu Kang ,  Tae-Yeong Kim ,  Byung-Lyul Park ,  Jum-Yong Park ,  Kyu-Ha Lee ,  Deok-Young Jung ,  Gil-Heyun Choi

IPC: H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/06181 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/12044 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A fabricating method for a semiconductor device is provided. The fabricating method includes providing a first wafer, forming a sacrificial layer on the first wafer, forming a release layer on the sacrificial layer, forming an adhesive layer on the release layer, and placing a second wafer on the adhesive layer and bonding the first wafer to the second wafer.

Abstract translation: 提供了一种用于半导体器件的制造方法。 制造方法包括提供第一晶片，在第一晶片上形成牺牲层，在牺牲层上形成剥离层，在剥离层上形成粘合剂层，将第二晶片放置在粘合剂层上，并将第一晶片 到第二晶片。

公开(公告)号：US09865581B2

公开(公告)日：2018-01-09

申请号：US14940621

申请日：2015-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo-Hee Jang ,  Pil-Kyu Kang ,  Seok-Ho Kim ,  Tae-Yeong Kim ,  Hyo-Ju Kim ,  Byung-Lyul Park ,  Jum-Yong Park ,  Jin-Ho An ,  Kyu-Ha Lee ,  Yi-Koan Hong

IPC: H01L25/00 ,  H01L23/532 ,  H01L21/768 ,  H01L27/146

CPC classification number: H01L25/50 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/1469 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08121 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/04941 ,  H01L2924/04953

Abstract: A first insulating layer is formed on a substrate. An opening is formed in the first insulating layer. A barrier layer is formed on the first insulating layer and conforming to sidewalls of the first insulating layer in the opening, and a conductive layer is formed on the barrier layer. Chemical mechanical polishing is performed to expose the first insulating layer and leave a barrier layer pattern in the opening and a conductive layer pattern on the barrier layer pattern in the opening, wherein a portion of the conductive layer pattern protrudes above an upper surface of the insulating layer and an upper surface of the barrier layer pattern. A second insulating layer is formed on the first insulating layer, the barrier layer pattern and the conductive layer pattern and planarized to expose the conductive layer pattern. A second substrate may be bonded to the exposed conductive layer pattern.

公开(公告)号：US09236349B2

公开(公告)日：2016-01-12

申请号：US13943828

申请日：2013-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Ha Lee ,  Pil-Kyu Kang ,  Tae-Yeong Kim ,  Ho-Jin Lee ,  Byung-Lyul Park ,  Gil-Heyun Choi

IPC: H01L23/538 ,  H01L23/485 ,  H01L23/48 ,  H01L23/00 ,  H01L21/683 ,  H01L21/768 ,  H01L23/525 ,  H01L23/532

CPC classification number: H01L23/5384 ,  H01L21/6836 ,  H01L21/76834 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/525 ,  H01L23/53238 ,  H01L24/00 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/06182 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01074

Abstract: Semiconductor device including through via structure and redistribution structures is provided. The semiconductor device may include internal circuits on a first side of a substrate, a through via structure vertically penetrating the substrate to be electrically connected to one of the internal circuits, a redistribution structure on a second side of the substrate and electrically connected to the through via structure, and an insulating layer between the second side of the substrate and the redistribution structure. The redistribution structure may include a redistribution barrier layer and a redistribution metal layer, and the redistribution barrier layer may extend on a bottom surface of the redistribution metal layer and may partially surround a side of the redistribution metal layer.

Abstract translation: 提供了包括通孔结构和再分配结构的半导体器件。 半导体器件可以包括在衬底的第一侧上的内部电路，垂直穿过衬底以与内部电路中的一个电连接的通孔结构，在衬底的第二侧上的再分配结构，并且电连接到通孔 通孔结构，以及在基板的第二面和再分布结构之间的绝缘层。 再分布结构可以包括再分配阻挡层和再分布金属层，再分布阻挡层可以在再分布金属层的底表面上延伸并且可以部分地围绕再分布金属层的一侧。

公开(公告)号：US11640912B2

公开(公告)日：2023-05-02

申请号：US16507407

申请日：2019-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun-Hyung Kim ,  Sung-Hyup Kim ,  Tae-Yeong Kim

IPC: H01L21/67 ,  H01L23/00 ,  H01L21/687 ,  H01L21/673 ,  H01L25/00

Abstract: A substrate bonding apparatus includes a substrate susceptor to support a first substrate, a substrate holder over the substrate susceptor to hold a second substrate, the substrate holder including a plurality of independently moveable holding fingers, and a chamber housing to accommodate the substrate susceptor and the substrate holder.

公开(公告)号：US10906283B2

公开(公告)日：2021-02-02

申请号：US16387032

申请日：2019-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Yeong Kim ,  Jun-Hyung Kim ,  Hoe-Chul Kim ,  Hoon-Joo Na ,  Kwang-Jin Moon

IPC: B32B37/00 ,  H01L21/687 ,  B32B37/10

Abstract: A wafer bonding apparatus including: a lower chuck to which a lower wafer is secured at a peripheral portion of the lower chuck; an upper chuck to which an upper wafer is secured; a bonding initiator for pressuring a central portion of the upper wafer until the central portion of the upper wafer reaches a central portion of the lower wafer, thereby initiating a bonding process of the upper and the lower wafers by deforming the upper wafer; and a bonding controller for controlling a bonding speed between a peripheral portion of the upper wafer and a peripheral portion of the lower wafer such that the upper wafer becomes un-deformed prior to bonding the peripheral portion of the upper wafer and the peripheral portion of the lower wafer.

公开(公告)号：US09520361B2

公开(公告)日：2016-12-13

申请号：US14937406

申请日：2015-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pil-Kyu Kang ,  Seok-Ho Kim ,  Tae-Yeong Kim ,  Hyo-Ju Kim ,  Byung-Lyul Park ,  Joo-Hee Jang ,  Jin-Ho Chun

IPC: H01L23/532 ,  H01L25/065

CPC classification number: H01L23/53228 ,  H01L21/76843 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L25/0657 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/08121 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate, a first conductive structure on the substrate, and a second conductive structure on the first conductive structure. The semiconductor device includes first and second metal-diffusion-blocking layers on respective sidewalls of the first and second conductive structures. The semiconductor device includes an insulating layer between the first and second metal-diffusion-blocking layers. Moreover, the semiconductor device includes a metal-diffusion-shield pattern in the insulating layer and spaced apart from the first conductive structure.

Abstract translation: 提供半导体器件。 半导体器件包括衬底，衬底上的第一导电结构和第一导电结构上的第二导电结构。 半导体器件包括在第一和第二导电结构的相应侧壁上的第一和第二金属扩散阻挡层。 半导体器件包括在第一和第二金属扩散阻挡层之间的绝缘层。 此外，半导体器件在绝缘层中包括金属扩散屏蔽图案并且与第一导电结构间隔开。

公开(公告)号：US20160141249A1

公开(公告)日：2016-05-19

申请号：US14937406

申请日：2015-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pil-Kyu Kang ,  Seok-Ho Kim ,  Tae-Yeong Kim ,  Hyo-Ju Kim ,  Byung-Lyul Park ,  Joo-Hee Jang ,  Jin-Ho Chun

IPC: H01L23/532 ,  H01L25/065

CPC classification number: H01L23/53228 ,  H01L21/76843 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L25/0657 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/08121 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate, a first conductive structure on the substrate, and a second conductive structure on the first conductive structure. The semiconductor device includes first and second metal-diffusion-blocking layers on respective sidewalls of the first and second conductive structures. The semiconductor device includes an insulating layer between the first and second metal-diffusion-blocking layers. Moreover, the semiconductor device includes a metal-diffusion-shield pattern in the insulating layer and spaced apart from the first conductive structure.

Abstract translation: 提供半导体器件。 半导体器件包括衬底，衬底上的第一导电结构和第一导电结构上的第二导电结构。 半导体器件包括在第一和第二导电结构的相应侧壁上的第一和第二金属扩散阻挡层。 半导体器件包括在第一和第二金属扩散阻挡层之间的绝缘层。 此外，半导体器件在绝缘层中包括金属扩散屏蔽图案并且与第一导电结构间隔开。

公开(公告)号：US10763243B2

公开(公告)日：2020-09-01

申请号：US16135122

申请日：2018-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Hyung Kim ,  Sung-Hyup Kim ,  Kyeong-Bin Lim ,  Seok-Ho Kim ,  Tae-Yeong Kim

IPC: H01L25/065 ,  H01L21/67 ,  H01L25/00 ,  H01L21/66 ,  H01L21/687 ,  H01L21/68

Abstract: A substrate bonding apparatus and a method of bonding substrates, the apparatus including an upper chuck securing a first substrate onto a lower surface thereof such that the first substrate is downwardly deformed into a concave surface profile; a lower chuck arranged under the upper chuck and securing a second substrate onto an upper surface thereof such that the second substrate is upwardly deformed into a convex surface profile; and a chuck controller controlling the upper chuck and the lower chuck to secure the first substrate and the second substrate, respectively, and generating a shape parameter for changing a shape of the second substrate to the convex surface profile from a flat surface profile.