公开(公告)号：US10446774B2

公开(公告)日：2019-10-15

申请号：US15870922

申请日：2018-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yi-Koan Hong ,  Kwang-Jin Moon ,  Nae-In Lee ,  Ho-Jin Lee

IPC: H01L23/48 ,  H01L51/44 ,  H01L25/065 ,  H01L23/532 ,  H01L23/538 ,  H01L21/768 ,  H01L51/00 ,  H01L23/00 ,  B82Y99/00 ,  B82Y10/00

Abstract: A semiconductor device includes a first conductive pattern at an upper portion of a first insulating interlayer on a first substrate, a first plurality of conductive nanotubes (CNTs) extending vertically, a second conductive pattern at a lower portion of a second insulating interlayer beneath a second substrate, and a second plurality of CNTs extending vertically. A lower surface of the second insulating interlayer contacts an upper surface of the first insulating interlayer. At least a portion of a sidewall of each of the first plurality of CNTs is covered by the first conductive pattern, and at least a portion of a sidewall of each of the second plurality of CNTs is covered by the second conductive pattern. The first and second conductive patterns vertically face each other, and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.

公开(公告)号：US09653623B2

公开(公告)日：2017-05-16

申请号：US14956382

申请日：2015-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yi-Koan Hong ,  Yeun-Sang Park ,  Byung-Lyul Park ,  Joo-Hee Jang

IPC: H01L31/02 ,  H01L31/0232 ,  H01L23/00

CPC classification number: H01L31/02005 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/91 ,  H01L31/02327 ,  H01L2224/04026 ,  H01L2224/05547 ,  H01L2224/05557 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06505 ,  H01L2224/06517 ,  H01L2224/08121 ,  H01L2224/08147 ,  H01L2224/27416 ,  H01L2224/27602 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29014 ,  H01L2224/29022 ,  H01L2224/2929 ,  H01L2224/30051 ,  H01L2224/3013 ,  H01L2224/3014 ,  H01L2224/3015 ,  H01L2224/3016 ,  H01L2224/32147 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80903 ,  H01L2224/83193 ,  H01L2224/8388 ,  H01L2924/00014

Abstract: In a method for fabricating a semiconductor, a first conductive pattern structure partially protruding upwardly from first insulating interlayer is formed in first insulating interlayer. A first bonding insulation layer pattern covering the protruding portion of first conductive pattern structure is formed on first insulating interlayer. A first adhesive pattern containing a polymer is formed on first bonding insulation layer pattern to fill a first recess formed on first bonding insulation layer pattern. A second bonding insulation layer pattern covering the protruding portion of second conductive pattern structure is formed on second insulating interlayer. A second adhesive pattern containing a polymer is formed on second bonding insulation layer pattern to fill a second recess formed on second bonding insulation layer pattern. The first and second adhesive patterns are melted. The first and second substrates are bonded with each other so that the conductive pattern structures contact each other.

公开(公告)号：US10978655B2

公开(公告)日：2021-04-13

申请号：US16562434

申请日：2019-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yi-Koan Hong ,  Kwang-Jin Moon ,  Nae-In Lee ,  Ho-Jin Lee

IPC: H01L23/485 ,  H01L51/44 ,  H01L25/065 ,  H01L23/532 ,  H01L23/538 ,  H01L23/00 ,  H01L51/00 ,  H01L21/768 ,  H01L25/00 ,  B82Y99/00 ,  B82Y10/00 ,  H01L25/18 ,  H01L27/146

Abstract: A semiconductor device includes a first conductive pattern at an upper portion of a first insulating interlayer on a first substrate, a first plurality of conductive nanotubes (CNTs) extending vertically, a second conductive pattern at a lower portion of a second insulating interlayer beneath a second substrate, and a second plurality of CNTs extending vertically. A lower surface of the second insulating interlayer contacts an upper surface of the first insulating interlayer. At least a portion of a sidewall of each of the first plurality of CNTs is covered by the first conductive pattern, and at least a portion of a sidewall of each of the second plurality of CNTs is covered by the second conductive pattern. The first and second conductive patterns vertically face each other, and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.

公开(公告)号：US20160141282A1

公开(公告)日：2016-05-19

申请号：US14940621

申请日：2015-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo-Hee Jang ,  Pil-Kyu Kang ,  Seok-Ho Kim ,  Tae-Yeong Kim ,  Hyo-Ju Kim ,  Byung-Lyul Park ,  Jum-Yong Park ,  Jin-Ho An ,  Kyu-Ha Lee ,  Yi-Koan Hong

IPC: H01L25/00 ,  H01L21/321

CPC classification number: H01L25/50 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/1469 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08121 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/04941 ,  H01L2924/04953

Abstract: A first insulating layer is formed on a substrate. An opening is formed in the first insulating layer. A barrier layer is formed on the first insulating layer and conforming to sidewalls of the first insulating layer in the opening, and a conductive layer is formed on the barrier layer. Chemical mechanical polishing is performed to expose the first insulating layer and leave a barrier layer pattern in the opening and a conductive layer pattern on the barrier layer pattern in the opening, wherein a portion of the conductive layer pattern protrudes above an upper surface of the insulating layer and an upper surface of the barrier layer pattern. A second insulating layer is formed on the first insulating layer, the barrier layer pattern and the conductive layer pattern and planarized to expose the conductive layer pattern. A second substrate may be bonded to the exposed conductive layer pattern.

Abstract translation: 在基板上形成第一绝缘层。 在第一绝缘层中形成开口。 阻挡层形成在第一绝缘层上并与开口中的第一绝缘层的侧壁一致，并且在阻挡层上形成导电层。 执行化学机械抛光以露出第一绝缘层并在开口中留下阻挡层图案，并且在开口中的阻挡层图案上具有导电层图案，其中导电层图案的一部分突出于绝缘体的上表面上方 层和阻挡层图案的上表面。 在第一绝缘层，阻挡层图案和导电层图案上形成第二绝缘层，并平坦化以暴露导电层图案。 第二衬底可以结合到暴露的导电层图案。

公开(公告)号：US09865581B2

公开(公告)日：2018-01-09

申请号：US14940621

申请日：2015-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo-Hee Jang ,  Pil-Kyu Kang ,  Seok-Ho Kim ,  Tae-Yeong Kim ,  Hyo-Ju Kim ,  Byung-Lyul Park ,  Jum-Yong Park ,  Jin-Ho An ,  Kyu-Ha Lee ,  Yi-Koan Hong

IPC: H01L25/00 ,  H01L23/532 ,  H01L21/768 ,  H01L27/146

CPC classification number: H01L25/50 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/1469 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08121 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/04941 ,  H01L2924/04953

Abstract: A first insulating layer is formed on a substrate. An opening is formed in the first insulating layer. A barrier layer is formed on the first insulating layer and conforming to sidewalls of the first insulating layer in the opening, and a conductive layer is formed on the barrier layer. Chemical mechanical polishing is performed to expose the first insulating layer and leave a barrier layer pattern in the opening and a conductive layer pattern on the barrier layer pattern in the opening, wherein a portion of the conductive layer pattern protrudes above an upper surface of the insulating layer and an upper surface of the barrier layer pattern. A second insulating layer is formed on the first insulating layer, the barrier layer pattern and the conductive layer pattern and planarized to expose the conductive layer pattern. A second substrate may be bonded to the exposed conductive layer pattern.

公开(公告)号：US09431341B2

公开(公告)日：2016-08-30

申请号：US14329749

申请日：2014-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yi-Koan Hong ,  Byung-Lyul Park ,  Ji-Soon Park ,  Si-Young Choi

IPC: H01L29/40 ,  H01L23/528 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/528 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/08146 ,  H01L2224/80894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: Provided is a semiconductor device. The semiconductor device includes a passivation layer defining a metal pattern on a first surface of a substrate, an inter-layer insulating layer disposed on a second surface of the substrate, and a piezoelectric pattern formed between the metal pattern and the passivation layer on the first surface of the substrate. A through-silicon-via and/or a pad can be directly bonded to another through-silicon-via and/or another pad by applying pressure only, and without performing a heat process.

Abstract translation: 提供一种半导体器件。 半导体器件包括在衬底的第一表面上限定金属图案的钝化层，设置在衬底的第二表面上的层间绝缘层，以及形成在金属图案和第一钝化层之间的压电图案 基板的表面。 通过硅通孔和/或焊盘可以仅通过施加压力而不进行热处理直接结合到另一个通硅通孔和/或另一焊盘。