公开(公告)号：US20150048522A1

公开(公告)日：2015-02-19

申请号：US14291698

申请日：2014-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soojae PARK ,  Hyunsuk CHUN

IPC: H01L23/00 ,  H01L25/07

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L23/3121 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/06135 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on the first semiconductor chip to expose at least a portion of the first semiconductor chip, and a stress-relieving structure provided at an edge of the first semiconductor chip and configured to relieve stress applied between the first semiconductor chip and the second semiconductor chip.

Abstract translation: 半导体封装包括封装基板，安装在封装基板上的第一半导体芯片，安装在第一半导体芯片上以暴露第一半导体芯片的至少一部分的第二半导体芯片，以及设置在边缘的应力消除结构 并且被配置为减轻施加在第一半导体芯片和第二半导体芯片之间的应力。

公开(公告)号：US20170194240A1

公开(公告)日：2017-07-06

申请号：US15385062

申请日：2016-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojae PARK ,  Kyujin LEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48624 ,  H01L2224/48824 ,  H01L2224/73265 ,  H01L2224/85423 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05432 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A package substrate including an insulating layer having a top surface and a bottom surface opposite to the top surface, at least one first copper pattern disposed in the insulating layer and adjacent to the top surface of the insulating layer, at least one second copper pattern disposed on the bottom surface of the insulating layer, and at least one embedded aluminum pad disposed on the at least one first copper pattern, the at least one embedded aluminum pad disposed in the insulating layer such that a top surface of the at least one embedded aluminum pad is exposed by the insulating layer may be provided.

公开(公告)号：US20160329275A1

公开(公告)日：2016-11-10

申请号：US15146664

申请日：2016-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojae PARK ,  Moon Gi CHO

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L24/48 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/45 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/85395 ,  H01L2224/85424 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/01029 ,  H01L2924/013 ,  H01L2924/01014 ,  H01L2924/00013

Abstract: The present inventive concept provides a package substrate. The package substrate comprises an insulating substrate having a top surface a circuit pattern disposed on the top surface, and a multilayer conductive joint unit disposed on the circuit pattern. The multilayer conductive joint unit comprises a nickel layer which is in contact with the circuit pattern, and an aluminum layer disposed on the nickel layer and connected to a semiconductor chip mounted on the insulating substrate.

Abstract translation: 本发明构思提供一种封装衬底。 封装衬底包括绝缘衬底，其具有设置在顶表面上的电路图案的顶表面和布置在电路图案上的多层导电接头单元。 多层导电接头单元包括与电路图案接触的镍层和设置在镍层上并连接到安装在绝缘基板上的半导体芯片的铝层。

公开(公告)号：US20180211909A1

公开(公告)日：2018-07-26

申请号：US15926287

申请日：2018-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojae PARK ,  Kyujin Lee

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48624 ,  H01L2224/48824 ,  H01L2224/73265 ,  H01L2224/85423 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05432 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A package substrate including an insulating layer having a top surface and a bottom surface opposite to the top surface, at least one first copper pattern disposed in the insulating layer and adjacent to the top surface of the insulating layer, at least one second copper pattern disposed on the bottom surface of the insulating layer, and at least one embedded aluminum pad disposed on the at least one first copper pattern, the at least one embedded aluminum pad disposed in the insulating layer such that a top surface of the at least one embedded aluminum pad is exposed by the insulating layer may be provided.