公开(公告)号：US09136255B2

公开(公告)日：2015-09-15

申请号：US14196577

申请日：2014-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun-Kyoung Seo ,  Eun-Jin Choi

IPC: H01L25/11 ,  H01L21/56 ,  H01L23/31 ,  H01L23/467 ,  H01L23/498 ,  H01L25/10 ,  H01L25/16 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/117 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/467 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29387 ,  H01L2224/294 ,  H01L2224/29486 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/13099

Abstract: A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.

Abstract translation: 封装堆叠结构包括在下封装基板上的下半导体芯片，具有多个下通孔插头焊盘，下封装件具有围绕下封装衬底的顶表面的一部分的下模塑料和下半导体的侧表面 芯片，上部封装基板上的上部半导体芯片，具有多个上部通孔插头焊盘，上部封装具有覆盖上部半导体芯片的上部模塑料，通过垂直穿过下部模塑料的插头，连接下部和 分别通过插塞接头和上部封装基板的底面之间的紧固元件和空气间隔。

公开(公告)号：US20140232005A1

公开(公告)日：2014-08-21

申请号：US14266836

申请日：2014-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Wook Yoo ,  Sun-Kyoung Seo

IPC: H01L23/00 ,  H01L23/492

CPC classification number: H01L24/30 ,  H01L23/3128 ,  H01L23/492 ,  H01L23/49816 ,  H01L24/10 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Provided are a stacked package, a method of fabricating a stacked package, and a method of mounting the stacked package fabricated by the same. The method of fabricating a stacked package includes providing an upper semiconductor package including an upper package substrate, upper semiconductor chips formed on a top surface of the upper package substrate, and first solders formed on a bottom surface of the upper package substrate and having a first melting temperature, providing a lower semiconductor package including a lower package substrate, lower semiconductor chips formed on a top surface of the lower package substrate, and solder paste nodes formed on the top surface of the lower package substrate and having a second melting temperature lower than the first melting temperature, and forming inter-package bonding units by attaching respective first solders and solder paste nodes to each other by performing annealing at a temperature higher than the second melting temperature and lower than the first melting temperature.

Abstract translation: 提供堆叠封装，制造堆叠封装的方法以及安装由其制造的堆叠封装的方法。 制造堆叠封装的方法包括提供上半导体封装，其包括上封装衬底，形成在上封装衬底的顶表面上的上半导体芯片和形成在上封装衬底的底表面上的第一焊料，并且具有第一 提供下半导体封装，其包括下封装衬底，形成在下封装衬底的顶表面上的下半导体芯片，以及形成在下封装衬底的顶表面上并具有低于 第一熔融温度，并且通过在高于第二熔融温度并低于第一熔融温度的温度下进行退火将各自的第一焊料和焊膏结点彼此连接来形成封装间接合单元。