公开(公告)号：US20190068311A1

公开(公告)日：2019-02-28

申请号：US16173786

申请日：2018-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo-Yol PARK ,  Yun-Seok CHOI

IPC: H04L1/00

Abstract: A method and apparatus are provided for controlling a data rate in a mobile communication system. The method includes changing an offset from a first offset used in a previous packet to a second offset determined based on whether or not the previous packet is successfully received by a second apparatus; determining whether or not a second channel quality in which the second offset is applied is within a range from a minimum quality to a maximum quality; if it is determined that the second channel quality is not within the range, determining that the offset is maintained as the first offset in a current packet; and transmitting, to the second apparatus, the current packet according to a first channel quality in which the first offset is applied.

公开(公告)号：US20140217616A1

公开(公告)日：2014-08-07

申请号：US14167989

申请日：2014-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Seok CHOI

IPC: H01L25/07 ,  H01L25/00

CPC classification number: H01L25/50 ,  H01L22/14 ,  H01L22/20 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L24/81 ,  H01L24/03 ,  H01L2224/81 ,  H01L2224/03

Abstract: A stack package includes a first semiconductor chip having a plurality of first pads, and a second semiconductor chip stacked on the first semiconductor chip and having a plurality of second pads corresponding to the first pads respectively, the second pads connected to the corresponding first pads. The first and second pads are arranged such that the first and second pads overlap with each other even after the first and second semiconductor chips are rotated relative to each other by a predetermined angle.

Abstract translation: 堆叠封装包括具有多个第一焊盘的第一半导体芯片和堆叠在第一半导体芯片上并且分别具有与第一焊盘对应的多个第二焊盘的第二半导体芯片，第二焊盘连接到对应的第一焊盘。 即使在第一和第二半导体芯片相对于彼此旋转预定角度之后，第一和第二焊盘被布置成使得第一焊盘和第二焊盘彼此重叠。

公开(公告)号：US20200312755A1

公开(公告)日：2020-10-01

申请号：US16529194

申请日：2019-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Seok CHOI

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538

Abstract: A semiconductor package includes a package substrate, an interposer on the package substrate, and a first semiconductor device and a second semiconductor device on the interposer, the first and second semiconductor devices connected to each other by the interposer, wherein at least one of the first semiconductor device and the second semiconductor device includes an overhang portion protruding from a sidewall of the interposer.

公开(公告)号：US20150188663A1

公开(公告)日：2015-07-02

申请号：US14584623

申请日：2014-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo-Yol PARK ,  Yun-Seok CHOI

IPC: H04L1/00

CPC classification number: H04L1/0002 ,  H04L1/0021

Abstract: Disclosed are an apparatus and system for controlling a data rate in a mobile communication system. The apparatus includes a controller which is configured to update an offset when an error rate of a channel needs to be corrected based on a code rate of a frame, presence/absence of an error through Cyclic Redundancy Check (CRC), and channel state information such as an offset value, and maintain the offset when the code rate of the channel is a maximum value or a minimum value.

Abstract translation: 公开了一种用于控制移动通信系统中的数据速率的装置和系统。 该装置包括：控制器，被配置为当基于帧的码率，通过循环冗余校验（CRC）的错误的存在/不存在以及信道状态信息需要校正信道的错误率时更新偏移量 例如偏移值，并且当信道的码率是最大值或最小值时保持偏移。

公开(公告)号：US20140367839A1

公开(公告)日：2014-12-18

申请号：US14475170

申请日：2014-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Seok CHOI ,  Tae-je CHO

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/11

Abstract: A semiconductor package includes a first semiconductor package, a second semiconductor package, and a package-connecting member. The first semiconductor package includes a first substrate, a chip stacking portion disposed on the first substrate and including a plurality of first semiconductor chips, and a first sealant for surrounding the chip stacking portion on the first substrate. The second semiconductor package includes a second substrate, at least one second semiconductor chip disposed on the second substrate, and a second sealant for surrounding the second semiconductor chip on the second substrate. The package-connecting member electrically connects the first semiconductor package and the second semiconductor package. The plurality of first semiconductor chips include a first chip including through silicon vias (TSVs) and a second chip electrically connected to the first chip via the TSVs, and the chip stacking portion includes an internal sealant for filling a space between the first chip and the second chip and extending to a side of the second chip.

Abstract translation: 半导体封装包括第一半导体封装，第二半导体封装和封装连接元件。 第一半导体封装包括第一衬底，设置在第一衬底上并包括多个第一半导体芯片的芯片堆叠部分，以及用于围绕第一衬底上的芯片堆叠部分的第一密封剂。 第二半导体封装包括第二衬底，设置在第二衬底上的至少一个第二半导体芯片和用于围绕第二衬底上的第二半导体芯片的第二密封剂。 封装连接部件电连接第一半导体封装和第二半导体封装。 多个第一半导体芯片包括通过硅通孔（TSV）的第一芯片和通过TSV与第一芯片电连接的第二芯片，并且芯片堆叠部分包括用于填充第一芯片和第二芯片之间的空间的内部密封剂 第二芯片并且延伸到第二芯片的一侧。

公开(公告)号：US20250014977A1

公开(公告)日：2025-01-09

申请号：US18897421

申请日：2024-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Seok CHOI

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/485 ,  H01L23/538

Abstract: A semiconductor package includes a package substrate, an interposer on the package substrate, and a first semiconductor device and a second semiconductor device on the interposer, the first and second semiconductor devices connected to each other by the interposer, wherein at least one of the first semiconductor device and the second semiconductor device includes an overhang portion protruding from a sidewall of the interposer.

公开(公告)号：US20230290711A1

公开(公告)日：2023-09-14

申请号：US18318864

申请日：2023-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Seok CHOI

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L23/485

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49838 ,  H01L23/49827 ,  H01L23/5386 ,  H01L24/33 ,  H01L23/4855

Abstract: A semiconductor package includes a package substrate, an interposer on the package substrate, and a first semiconductor device and a second semiconductor device on the interposer, the first and second semiconductor devices connected to each other by the interposer, wherein at least one of the first semiconductor device and the second semiconductor device includes an overhang portion protruding from a sidewall of the interposer.

公开(公告)号：US20160236318A1

公开(公告)日：2016-08-18

申请号：US15001410

申请日：2016-01-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun-Seok CHOI ,  Chang-Gil RYU ,  Geun-Young SONG ,  Ki-Yeon CHU ,  Jin-Suk HONG

IPC: B24B37/32

CPC classification number: B24B37/32 ,  B24B37/30 ,  B24B55/02

Abstract: A polishing head includes a substrate carrier to suck and to pressurize a substrate, and a retainer ring secured under the substrate carrier, the retainer ring surrounding a circumference of the substrate and including a cooling channel therethrough to circulate a coolant fluid.

Abstract translation: 抛光头包括用于吸附和加压基板的基板载体，以及固定在基板载体下方的保持环，保持环围绕基板的圆周并且包括通过其的冷却通道以循环冷却剂流体。

公开(公告)号：US20150221616A1

公开(公告)日：2015-08-06

申请号：US14688679

申请日：2015-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Seok CHOI

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16113 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2224/16145

Abstract: A semiconductor package having a first semiconductor device including an active surface and a non-active surface opposite to the active surface, and a second semiconductor device having an active surface facing the active surface of the first semiconductor device is provided. Connection terminals are provided on the active surface of the second semiconductor device and first through vias are provided in the first semiconductor device. External terminals providing electrical connection with an external device are provided. The connection terminals comprise center terminals overlapping with the active surface of the first semiconductor device and outer terminals around the center terminals. The center terminals are electrically connected to the external terminals through the first through via.

Abstract translation: 一种具有第一半导体器件的半导体封装，其具有包括有源面和与该有源面相反的非有源面的第一半导体器件，以及具有与第一半导体器件的有源面相对的有源面的第二半导体器件。 连接端子设置在第二半导体器件的有源表面上，并且第一通孔设置在第一半导体器件中。 提供了与外部设备电连接的外部端子。 连接端子包括与第一半导体器件的有源表面重叠的中心端子和围绕中心端子的外部端子。 中心端子通过第一通孔电连接到外部端子。

公开(公告)号：US20130175702A1

公开(公告)日：2013-07-11

申请号：US13738322

申请日：2013-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun-Seok CHOI ,  Tae-je CHO

IPC: H01L23/48

CPC classification number: H01L25/0652 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/11

Abstract: A semiconductor package includes a first semiconductor package, a second semiconductor package, and a package-connecting member. The first semiconductor package includes a first substrate, a chip stacking portion disposed on the first substrate and including a plurality of first semiconductor chips, and a first sealant for surrounding the chip stacking portion on the first substrate. The second semiconductor package includes a second substrate, at least one second semiconductor chip disposed on the second substrate, and a second sealant for surrounding the second semiconductor chip on the second substrate. The package-connecting member electrically connects the first semiconductor package and the second semiconductor package. The plurality of first semiconductor chips include a first chip including through silicon vias (TSVs) and a second chip electrically connected to the first chip via the TSVs, and the chip stacking portion includes an internal sealant for filling a space between the first chip and the second chip and extending to a side of the second chip.

Abstract translation: 半导体封装包括第一半导体封装，第二半导体封装和封装连接元件。 第一半导体封装包括第一衬底，设置在第一衬底上并包括多个第一半导体芯片的芯片堆叠部分，以及用于围绕第一衬底上的芯片堆叠部分的第一密封剂。 第二半导体封装包括第二衬底，设置在第二衬底上的至少一个第二半导体芯片和用于围绕第二衬底上的第二半导体芯片的第二密封剂。 封装连接部件电连接第一半导体封装和第二半导体封装。 多个第一半导体芯片包括通过硅通孔（TSV）的第一芯片和通过TSV与第一芯片电连接的第二芯片，并且芯片堆叠部分包括用于填充第一芯片和第二芯片之间的空间的内部密封剂 第二芯片并且延伸到第二芯片的一侧。