公开(公告)号：US06833619B1

公开(公告)日：2004-12-21

申请号：US10425134

申请日：2003-04-28

申请人： Sang Jae Jang ,  Sun Goo Lee ,  Sung Su Park ,  Sung Soon Park

发明人： Sang Jae Jang ,  Sun Goo Lee ,  Sung Su Park ,  Sung Soon Park

IPC分类号： H01L2334

CPC分类号： H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/743 ,  H01L24/83 ,  H01L2224/05599 ,  H01L2224/27013 ,  H01L2224/2919 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/743 ,  H01L2224/83051 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package has a substrate comprising a resin layer of an approximate planar plate, a cavity passing through the resin layer vertically at a center area thereof, a plurality of electrically conductive patterns formed at a bottom surface of the resin layer, and a conductive plan. An adhesive layer of a predetermined thickness is formed at an upper part of an inside of the cavity. A semiconductor die is positioned inside the cavity of the substrate and has a plurality of bond pads formed at a bottom surface thereof, a bottom surface of the adhesive layer being bonded to a top surface thereof. A plurality of conductive wires for electrically connecting the bond pads of the semiconductor die to the electrically conductive patterns are formed at a bottom surface of the substrate. An encapsulant is used for covering the semiconductor die formed at the lower part of the adhesive layer, the conductive wires and the cavity. A plurality of solder balls are fused to the electrically conductive patterns, which is formed at the bottom surface of the substrate.

摘要翻译： 半导体封装具有包括近似平板的树脂层，在其中心区域垂直穿过树脂层的空腔，形成在树脂层的底面的多个导电图案的基板，以及导电图 。 在空腔的内部的上部形成预定厚度的粘合剂层。 半导体管芯位于衬底的腔内部，并且在其底表面上形成有多个接合焊盘，粘合剂层的底表面粘合到其顶表面。 在基板的底面形成有用于将半导体管芯的接合焊盘电连接到导电图案的多个导线。 密封剂用于覆盖形成在粘合剂层的下部，导电线和空腔的半导体管芯。 多个焊球与形成在基板的底面的导电图案熔合。

公开(公告)号：US06750545B1

公开(公告)日：2004-06-15

申请号：US10376988

申请日：2003-02-28

申请人： Sun Goo Lee ,  Sang Jae Jang ,  Choon Heung Lee ,  Akito Yoshida

发明人： Sun Goo Lee ,  Sang Jae Jang ,  Choon Heung Lee ,  Akito Yoshida

IPC分类号： H01L2348

CPC分类号： H01L23/49805 ,  H01L23/49833 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/01079

摘要： A stackable semiconductor package. The semiconductor package comprises a plurality of first and second leads which are arranged in a generally quadrangular array having one pair of opposed sides defined by the first leads and one pair of opposed sides defined by the second leads. The first and second leads each include opposed, generally planar first and second surfaces, and a third surface which is also disposed in opposed relation to the second surface and positioned between the first and second surfaces. A first semiconductor die is electrically connected to the third surfaces of the first leads, with a second semiconductor die being electrically connected to the third surfaces of the second leads. A package body at least partially encapsulates the first and second leads and the first and second semiconductor dies such that the first and second surfaces of each of the first and second leads are exposed in the package body.

摘要翻译： 可堆叠半导体封装。 半导体封装包括多个第一和第二引线，其布置成大致四边形阵列，其具有由第一引线限定的一对相对侧和由第二引线限定的一对相对侧。 第一和第二引线各自包括相对的，大致平面的第一和第二表面，以及第三表面，其也与第二表面相对设置并且位于第一和第二表面之间。 第一半导体管芯电连接到第一引线的第三表面，第二半导体管芯电连接到第二引线的第三表面。 封装体至少部分地封装第一和第二引线以及第一和第二半导体管芯，使得第一和第二引线中的每一个的第一和第二表面暴露在封装主体中。

公开(公告)号：US06995459B2

公开(公告)日：2006-02-07

申请号：US11063299

申请日：2005-02-22

申请人： Choon Heung Lee ,  Donald C. Foster ,  Jeoung Kyu Choi ,  Wan Jong Kim ,  Kyong Hoon Youn ,  Sang Ho Lee ,  Sun Goo Lee

发明人： Choon Heung Lee ,  Donald C. Foster ,  Jeoung Kyu Choi ,  Wan Jong Kim ,  Kyong Hoon Youn ,  Sang Ho Lee ,  Sun Goo Lee

IPC分类号： H01L23/495

CPC分类号： H01L24/49 ,  H01L23/3107 ,  H01L23/49503 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2221/68377 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： In accordance with the present invention, there is provided a semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and including at least two slots formed therein and extending along respective ones of a pair of the peripheral edge segments thereof. The semiconductor package further comprises a plurality of first leads which are segregated into at least two sets disposed within respective ones of the slots included in the die paddle. In addition to the first leads, the semiconductor package includes a plurality of second leads which are also segregated into at least two sets extending along respective ones of at least two peripheral edge segments of the die paddle in spaced relation thereto. Electrically connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of each of the first and second leads. At least portions of the die paddle, the first and second leads, and the semiconductor die are encapsulated by a package body, the bottom surfaces of the die paddle and the first leads being exposed in a common exterior surface of the package body.

摘要翻译： 根据本发明，提供了一种半导体封装，其包括限定多个外围边缘段的大致平坦的管芯片，并且包括形成在其中的至少两个槽，并沿其一对周边边缘段中的相应的一个延伸。 半导体封装还包括多个第一引线，它们分离成设置在包括在管芯焊盘中的各个槽中的至少两个组。 除了第一引线之外，半导体封装还包括多个第二引线，它们也分隔成至少两组，其间隔开的关系相对于管芯焊盘的至少两个周边边缘段的相应延伸。 电连接到管芯焊盘的顶表面的是至少一个半导体管芯，其电连接到第一和第二引线中的每一个的至少一些。 裸片，第一和第二引线和半导体管芯的至少一部分被封装主体封装，裸片焊盘的底表面和第一引线暴露在封装体的公共外表面中。

公开(公告)号：US06927483B1

公开(公告)日：2005-08-09

申请号：US10383504

申请日：2003-03-07

申请人： Sun Goo Lee ,  Choon Heung Lee ,  Sang Ho Lee

发明人： Sun Goo Lee ,  Choon Heung Lee ,  Sang Ho Lee

IPC分类号： H01L23/04 ,  H01L23/31 ,  H01L23/48 ,  H01L23/495 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/49 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16245 ,  H01L2224/29007 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48471 ,  H01L2224/4945 ,  H01L2224/73265 ,  H01L2224/85191 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18165 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/48227

摘要： A semiconductor package exhibiting efficient placement of semiconductor leads in a micro lead frame design is provided. An integrated circuit die is bonded to the top surfaces of leads, thereby allowing the leads to partially reside under the die. As a result, surface area on the bottom surface of the semiconductor package is recaptured. The die can be further bonded a die paddle if so desired. One or more channels can be cut into the bottom surface of the package in order to separate first and second leads. Such channels allow separate leads to be fabricated from a single lead member which is subsequently cut.

摘要翻译： 提供了一种在微引线框架设计中显示出半导体引线的有效放置的半导体封装。 集成电路管芯结合到引线的顶表面，从而允许引线部分地位于管芯下方。 结果，重新获得半导体封装的底表面上的表面积。 如果需要，模具可以进一步粘合模片。 可以将一个或多个通道切割到包装的底表面中，以分离第一和第二引线。 这样的通道允许单独的引线由随后切割的单个引线构件制造。

公开(公告)号：US06879034B1

公开(公告)日：2005-04-12

申请号：US10427118

申请日：2003-05-01

申请人： Jun Young Yang ,  Sun Goo Lee ,  Choon Heung Lee

发明人： Jun Young Yang ,  Sun Goo Lee ,  Choon Heung Lee

IPC分类号： H01L21/56 ,  H01L23/31 ,  H01L23/49 ,  H01L23/495 ,  H01L23/498 ,  H01L23/64 ,  H01L25/065 ,  H01L23/053

CPC分类号： H01L21/568 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49531 ,  H01L23/49861 ,  H01L23/64 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package comprising a low temperature co-fired ceramic substrate defining opposed top and bottom surfaces. The substrate comprises at least two stacked ceramic layers and electrically conductive patterns which extend between the layers and along the top surface of the substrate. Mounted to the top surface of the substrate and electrically connected to the conductive patterns is at least one semiconductor die. A plurality of leads extend at least partially about the substrate in spaced relation thereto. Each of the leads defines opposed top and bottom surfaces, the semiconductor die being electrically connected to at least one of the leads. A package body at least partially encapsulates the substrate, the semiconductor die and the leads such that at least a portion of the bottom surface of each of the leads is exposed in the package body.

摘要翻译： 一种半导体封装，包括限定相对的顶表面和底表面的低温共烧陶瓷衬底。 衬底包括至少两个堆叠的陶瓷层和在层之间并沿着衬底的顶表面延伸的导电图案。 安装到基板的顶表面并电连接到导电图案是至少一个半导体管芯。 多个引线至少部分地围绕基板间隔开地延伸。 每个引线限定相对的顶表面和底表面，半导体管芯电连接到至少一个引线。 封装体至少部分地封装衬底，半导体管芯和引线，使得每个引线的底表面的至少一部分暴露在封装主体中。

公开(公告)号：US06876068B1

公开(公告)日：2005-04-05

申请号：US10447012

申请日：2003-05-28

申请人： Choon Heung Lee ,  Donald C. Foster ,  Jeoung Kyu Choi ,  Wan Jong Kim ,  Kyong Hoon Youn ,  Sang Ho Lee ,  Sun Goo Lee

发明人： Choon Heung Lee ,  Donald C. Foster ,  Jeoung Kyu Choi ,  Wan Jong Kim ,  Kyong Hoon Youn ,  Sang Ho Lee ,  Sun Goo Lee

IPC分类号： H01L23/31 ,  H01L23/495

CPC分类号： H01L24/49 ,  H01L23/3107 ,  H01L23/49503 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2221/68377 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： In accordance with the present invention, there is provided a semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and including at least two slots formed therein and extending along respective ones of a pair of the peripheral edge segments thereof. The semiconductor package further comprises a plurality of first leads which are segregated into at least two sets disposed within respective ones of the slots included in the die paddle. In addition to the first leads, the semiconductor package includes a plurality of second leads which are also segregated into at least two sets extending along respective ones of at least two peripheral edge segments of the die paddle in spaced relation thereto. Electrically connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of each of the first and second leads. At least portions of the die paddle, the first and second leads, and the semiconductor die are encapsulated by a package body, the bottom surfaces of the die paddle and the first leads being exposed in a common exterior surface of the package body.

摘要翻译： 根据本发明，提供了一种半导体封装，其包括限定多个外围边缘段的大致平坦的管芯片，并且包括形成在其中的至少两个槽，并沿其一对周边边缘段中的相应的一个延伸。 半导体封装还包括多个第一引线，它们分离成设置在包括在管芯焊盘中的各个槽中的至少两个组。 除了第一引线之外，半导体封装还包括多个第二引线，它们也分隔成至少两组，其间隔开的关系相对于管芯焊盘的至少两个周边边缘段的相应延伸。 电连接到管芯焊盘的顶表面的是至少一个半导体管芯，其电连接到第一和第二引线中的每一个的至少一些。 裸片，第一和第二引线和半导体管芯的至少一部分被封装主体封装，裸片焊盘的底表面和第一引线暴露在封装体的公共外表面中。