公开(公告)号：US06833619B1

公开(公告)日：2004-12-21

申请号：US10425134

申请日：2003-04-28

申请人： Sang Jae Jang ,  Sun Goo Lee ,  Sung Su Park ,  Sung Soon Park

发明人： Sang Jae Jang ,  Sun Goo Lee ,  Sung Su Park ,  Sung Soon Park

IPC分类号： H01L2334

CPC分类号： H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/743 ,  H01L24/83 ,  H01L2224/05599 ,  H01L2224/27013 ,  H01L2224/2919 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/743 ,  H01L2224/83051 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package has a substrate comprising a resin layer of an approximate planar plate, a cavity passing through the resin layer vertically at a center area thereof, a plurality of electrically conductive patterns formed at a bottom surface of the resin layer, and a conductive plan. An adhesive layer of a predetermined thickness is formed at an upper part of an inside of the cavity. A semiconductor die is positioned inside the cavity of the substrate and has a plurality of bond pads formed at a bottom surface thereof, a bottom surface of the adhesive layer being bonded to a top surface thereof. A plurality of conductive wires for electrically connecting the bond pads of the semiconductor die to the electrically conductive patterns are formed at a bottom surface of the substrate. An encapsulant is used for covering the semiconductor die formed at the lower part of the adhesive layer, the conductive wires and the cavity. A plurality of solder balls are fused to the electrically conductive patterns, which is formed at the bottom surface of the substrate.

摘要翻译： 半导体封装具有包括近似平板的树脂层，在其中心区域垂直穿过树脂层的空腔，形成在树脂层的底面的多个导电图案的基板，以及导电图 。 在空腔的内部的上部形成预定厚度的粘合剂层。 半导体管芯位于衬底的腔内部，并且在其底表面上形成有多个接合焊盘，粘合剂层的底表面粘合到其顶表面。 在基板的底面形成有用于将半导体管芯的接合焊盘电连接到导电图案的多个导线。 密封剂用于覆盖形成在粘合剂层的下部，导电线和空腔的半导体管芯。 多个焊球与形成在基板的底面的导电图案熔合。

公开(公告)号：US06936922B1

公开(公告)日：2005-08-30

申请号：US10672886

申请日：2003-09-26

申请人： Sung Soon Park ,  Sang Jae Jang ,  Choon Heung Lee ,  Seon Goo Lee ,  Eun Sook Sohn ,  Sung Su Park

发明人： Sung Soon Park ,  Sang Jae Jang ,  Choon Heung Lee ,  Seon Goo Lee ,  Eun Sook Sohn ,  Sung Su Park

IPC分类号： H01L23/16 ,  H01L23/48 ,  H01L23/498 ,  H01L25/10 ,  H05K1/11 ,  H05K3/34

CPC分类号： H05K3/3436 ,  H01L23/16 ,  H01L23/49816 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/3511 ,  H05K1/111 ,  H05K2201/094 ,  H05K2201/09736 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An electrical substrate useful for semiconductor packages is disclosed. The electrical substrate includes a core insulative layer. A first surface of the insulative layer has circuit patterns thereon. Some of the circuit patterns are stepped in their heights from the first surface, in that a first subportion of the circuit pattern, including a ball land, extends further from the first surface than a second subportion of the same circuit pattern, and also extends further from the first surface than a ball land of other circuit patterns. Accordingly, solder balls fused to the ball lands of the stepped circuit patterns extend further from the first surface than same-size solder balls fused to the ball lands of the non-stepped circuit patterns, thereby circumventing electrical connectivity problems that may arise from warpage of the electrical substrate.

摘要翻译： 公开了一种可用于半导体封装的电气基板。 电气基板包括芯绝缘层。 绝缘层的第一表面具有电路图案。 电路图案中的一些从第一表面上升到它们的高度，因为电路图形的第一子部分（包括球形区域）比第一表面的第一子部分比相同电路图案的第二子部分进一步延伸，并且还进一步延伸 从第一个表面比其他电路图案的球场。 因此，熔融到阶梯式电路图案的球台的焊球比与非阶梯式电路图案的球面熔合的相同尺寸的焊球相比，从第一表面延伸出来，从而避免了由于翘曲引起的电连接问题 电气基板。

公开(公告)号：US06750545B1

公开(公告)日：2004-06-15

申请号：US10376988

申请日：2003-02-28

申请人： Sun Goo Lee ,  Sang Jae Jang ,  Choon Heung Lee ,  Akito Yoshida

发明人： Sun Goo Lee ,  Sang Jae Jang ,  Choon Heung Lee ,  Akito Yoshida

IPC分类号： H01L2348

CPC分类号： H01L23/49805 ,  H01L23/49833 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/01079

摘要： A stackable semiconductor package. The semiconductor package comprises a plurality of first and second leads which are arranged in a generally quadrangular array having one pair of opposed sides defined by the first leads and one pair of opposed sides defined by the second leads. The first and second leads each include opposed, generally planar first and second surfaces, and a third surface which is also disposed in opposed relation to the second surface and positioned between the first and second surfaces. A first semiconductor die is electrically connected to the third surfaces of the first leads, with a second semiconductor die being electrically connected to the third surfaces of the second leads. A package body at least partially encapsulates the first and second leads and the first and second semiconductor dies such that the first and second surfaces of each of the first and second leads are exposed in the package body.

摘要翻译： 可堆叠半导体封装。 半导体封装包括多个第一和第二引线，其布置成大致四边形阵列，其具有由第一引线限定的一对相对侧和由第二引线限定的一对相对侧。 第一和第二引线各自包括相对的，大致平面的第一和第二表面，以及第三表面，其也与第二表面相对设置并且位于第一和第二表面之间。 第一半导体管芯电连接到第一引线的第三表面，第二半导体管芯电连接到第二引线的第三表面。 封装体至少部分地封装第一和第二引线以及第一和第二半导体管芯，使得第一和第二引线中的每一个的第一和第二表面暴露在封装主体中。

公开(公告)号：US07220915B1

公开(公告)日：2007-05-22

申请号：US11060263

申请日：2005-02-17

申请人： Chul Woo Park ,  Sang Jae Jang ,  Sung Su Park ,  Choon Heung Lee ,  Suk Gu Ko

发明人： Chul Woo Park ,  Sang Jae Jang ,  Sung Su Park ,  Choon Heung Lee ,  Suk Gu Ko

IPC分类号： H05K3/28 ,  H01L23/02 ,  H01L23/495

CPC分类号： G11C29/48 ,  G11C29/1201 ,  H01L23/49855 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A memory card comprising a circuit board having opposed upper and lower circuit board surfaces, at least one test pad disposed on the upper circuit board surface, and a conductive pattern disposed on the lower circuit board surface and electrically connected to the test pad. Electrically connected to the conductive pattern of the circuit board is a leadframe which includes a plurality of leads, each of the leads having a signal pad portion. At least one electronic circuit element is attached to the lower circuit board surface and electrically connected to the leadframe and to the conductive pattern of the circuit board. A body at least partially encapsulates the circuit board, the leadframe and the electronic circuit element such that the test pad of the circuit board is exposed in an upper body surface of the body, and the signal pad portions of the leads of the leadframe are exposed in a lower body surface of the body.

摘要翻译： 一种存储卡，包括具有相对的上电路板表面和下电路板表面的电路板，设置在上电路板表面上的至少一个测试焊盘和布置在下电路板表面上并电连接到测试焊盘的导电图案。 电连接到电路板的导电图案的是引线框架，其包括多个引线，每个引线具有信号焊盘部分。 至少一个电子电路元件附接到下电路板表面并电连接到引线框架和电路板的导电图案。 主体至少部分地封装电路板，引线框架和电子电路元件，使得电路板的测试焊盘暴露在主体的上体表面中，并且引线框的引线的信号焊盘部分被暴露 在身体的下半身表面。

公开(公告)号：US07633763B1

公开(公告)日：2009-12-15

申请号：US10766101

申请日：2004-01-28

申请人： Chul Woo Park ,  Suk Gu Ko ,  Sang Jae Jang ,  Sung Su Park ,  Choon Heung Lee

发明人： Chul Woo Park ,  Suk Gu Ko ,  Sang Jae Jang ,  Sung Su Park ,  Choon Heung Lee

IPC分类号： H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC分类号： G06K19/07743 ,  G06K19/07724 ,  H01L2224/48091 ,  H01L2924/1815 ,  H05K1/117 ,  H05K3/284 ,  H05K2201/09036 ,  H05K2201/10159 ,  H05K2203/1316 ,  H05K2203/1572 ,  H01L2924/00014

摘要： A memory card comprising a substrate having opposed top and bottom surfaces and a plurality of terminals disposed on the bottom surface thereof. Mounted to the top surface of the substrate is at least one component which is itself electrically connected to the terminals of the substrate. Formed on the bottom surface of the substrate is a first encapsulation part. Formed on the top surface of the substrate is a second encapsulation part which encapsulates the component mounted thereto.

摘要翻译： 一种存储卡，包括具有相对的顶表面和底表面的基底和设置在其底表面上的多个端子。 安装到基板的顶表面的是至少一个本身电连接到基板的端子的部件。 形成在基板的底面上的是第一封装部。 形成在基板的顶表面上的是封装安装在其上的部件的第二封装部分。

公开(公告)号：US07201327B1

公开(公告)日：2007-04-10

申请号：US10967462

申请日：2004-10-18

申请人： Chul Woo Park ,  Sang Jae Jang ,  Sung Su Park ,  Choon Heung Lee ,  Suk Gu Ko

发明人： Chul Woo Park ,  Sang Jae Jang ,  Sung Su Park ,  Choon Heung Lee ,  Suk Gu Ko

IPC分类号： G06K19/06

CPC分类号： G06K19/077 ,  G06K19/07732 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00012

摘要： A memory card comprising a die paddle having opposed, generally planar first and second die paddle surfaces and multiple peripheral edge segments. Disposed along and in spaced relation to one of the peripheral edge segments of the die paddle is a plurality of contacts, each of which has opposed, generally planar first and second contact surfaces. An inner body partially encapsulates the die paddle and the contacts, the first contact surface of each of the contacts and the first die paddle surface of the die paddle being exposed in and substantially flush with a generally planar first inner body surface of the inner body. The inner body further defines a generally planar second inner body surface which is disposed in opposed relation to the first inner body surface, the second contact surface of each of the contacts being exposed in the second inner body surface. At least one electronic circuit element is attached to the first die paddle surface and electrically connected to at least one of the contacts. An outer body partially encapsulates the inner body such that the first die paddle surface, the first contact surface of each of the contacts, the first inner body surface and the electronic circuit element are covered by the outer body, with the second inner body surface and hence the second contact surface of each of the contacts not being covered by the outer body and thus exposed.

摘要翻译： 一种存储卡，其包括具有相对的，大致平面的第一和第二管芯片表面和多个外围边缘部分的管芯焊盘。 与模板的周边边缘部分中的一个相互间隔设置有多个触点，每个触点具有相对的大致平面的第一和第二接触表面。 内部主体部分地封装管芯焊盘和触头，每个触头的第一接触表面和管芯焊盘的第一裸片焊盘表面暴露于内部主体的大致平面的第一内部主体表面并基本上与其平齐。 内体进一步限定大致平坦的第二内体表面，其以与第一内体表面相对的方式设置，每个触头的第二接触表面暴露在第二内体表面中。 至少一个电子电路元件附接到第一裸片表面并电连接到至少一个触点。 外部主体部分地封装内部主体，使得第一裸片表面，每个触点的第一接触表面，第一内部主体表面和电子电路元件被外部主体覆盖，具有第二内部主体表面和 因此每个触点的第二接触表面不被外体覆盖并因此被暴露。

公开(公告)号：US07375975B1

公开(公告)日：2008-05-20

申请号：US11263428

申请日：2005-10-31

申请人： Sang Jae Jang ,  Chul Woo Park ,  Choon Heung Lee

发明人： Sang Jae Jang ,  Chul Woo Park ,  Choon Heung Lee

IPC分类号： H05K5/03 ,  H05K9/00

CPC分类号： G06K19/07745 ,  G06K19/07728 ,  G06K19/07732 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00

摘要： In accordance with the present invention, there is provided multiple embodiments of a memory card, each embodiment including a case which is cooperatively engaged to a module comprising at least a printed circuit board having an electronic circuit device mounted thereto. In each embodiment of the present invention, the case is reinforced by a stiffener which effectively increases the mechanical strength of the fully fabricated memory card, thus providing the capability to withstand typical bending and twisting tests. The stiffener may be provided in any one of a plurality of different shapes or profiles, and may embedded within one or more of various locations within the case.

摘要翻译： 根据本发明，提供了存储卡的多个实施例，每个实施例包括与至少包括安装有电子电路装置的印刷电路板的模块配合地接合的壳体。 在本发明的每个实施例中，通过加强件增强了外壳，该加强件有效地增加了完全制造的存储卡的机械强度，从而提供了经受典型的弯曲和扭曲试验的能力。 加强件可以以多种不同形状或轮廓中的任何一种形式提供，并且可以嵌入壳体内的各种位置的一个或多个中。

公开(公告)号：US07837120B1

公开(公告)日：2010-11-23

申请号：US11288906

申请日：2005-11-29

申请人： Sang Jae Jang ,  Chul Woo Park ,  Choon Heung Lee

发明人： Sang Jae Jang ,  Chul Woo Park ,  Choon Heung Lee

IPC分类号： G06K19/06

CPC分类号： G06K19/07732

摘要： In accordance with the present invention, there is provided multiple embodiments of a memory card, each embodiment including a module comprising at least a printed circuit board having an electronic circuit device mounted thereto. The module is inserted into a complementary cavity formed within a case of the memory card, such case generally defining the outer appearance of the memory card. The module is secured within the cavity of the case through the use of an adhesive. In each embodiment of the present invention, the module is uniquely configured to prevent adhesive leakage from within the corresponding cavity of the case of the memory card when the module is secured within the cavity.

摘要翻译： 根据本发明，提供了存储卡的多个实施例，每个实施例包括至少包括安装有电子电路装置的印刷电路板的模块。 模块被插入形成在存储卡的壳体内的互补空腔中，这种情况通常限定存储卡的外观。 模块通过使用粘合剂固定在外壳的腔内。 在本发明的每个实施例中，模块被独特地构造成当模块固定在空腔内时，防止粘合剂从存储卡的壳体的相应空腔内泄漏。

公开(公告)号：US20090021921A1

公开(公告)日：2009-01-22

申请号：US11114342

申请日：2005-04-26

申请人： Sang Jae Jang ,  Chul Woo Park ,  Suk Ku Ko ,  Choon Heung Lee

发明人： Sang Jae Jang ,  Chul Woo Park ,  Suk Ku Ko ,  Choon Heung Lee

IPC分类号： H05K1/14

CPC分类号： H05K3/284 ,  H01L23/3121 ,  H01L23/3135 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H05K1/0266 ,  H05K1/117 ,  H05K3/0052 ,  H05K2201/09145 ,  H05K2201/0989 ,  H05K2201/10159 ,  H05K2203/0191 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A memory card comprising a circuit board having opposed upper and lower circuit board surfaces, multiple side edges, a chamfer extending between a pair of the side edges, a plurality of pads disposed on the lower circuit board surface, and a conductive pattern which is disposed on the upper circuit board surface and electrically connected to the pads. At least one electronic circuit device is attached to the upper circuit board surface and electrically connected to the conductive pattern of the circuit board. A body at least partially encapsulates the circuit board and the electronic circuit element such that a section of the upper circuit board surface extending along the entirety of the chamfer is not covered by the body.

摘要翻译： 一种存储卡，包括具有相对的上电路板表面和下电路板表面的电路板，多个侧边缘，在一对侧边缘之间延伸的倒角，设置在下电路板表面上的多个焊盘和设置在下电路板表面上的导电图案 在上电路板表面上并电连接到焊盘。 至少一个电子电路装置附接到上电路板表面并电连接到电路板的导电图案。 主体至少部分地封装电路板和电子电路元件，使得沿整个倒角延伸的上部电路板表面的一部分不被主体覆盖。

公开(公告)号：US07359204B1

公开(公告)日：2008-04-15

申请号：US11355092

申请日：2006-02-15

申请人： Sang Jae Jang ,  Chul Woo Park ,  Jong Woon Choi ,  Jae Dong Kim ,  Choon Heung Lee ,  Chang Deok Lee

发明人： Sang Jae Jang ,  Chul Woo Park ,  Jong Woon Choi ,  Jae Dong Kim ,  Choon Heung Lee ,  Chang Deok Lee

IPC分类号： H05K7/20

CPC分类号： H05K5/0256 ,  G06K19/07 ,  G06K19/07732

摘要： A memory card including a module comprising at least a printed circuit board having an electronic circuit device mounted thereto and at least one I/O pad and at least one test pad disposed thereon. The module is inserted into a complementary cavity formed within a case of the memory card, such case generally defining the outer appearance of the memory card. The module is secured within the cavity of the case through the use of an adhesive. In each embodiment of the present invention, first and second covers are movably attached to a case for selectively covering or exposing the I/O pads and the test features/pads of the module of the memory card.

摘要翻译： 一种存储卡，包括至少包括安装有电子电路装置的印刷电路板和至少一个I / O焊盘和至少一个设置在其上的测试焊盘的模块。 模块被插入形成在存储卡的壳体内的互补空腔中，这种情况通常限定存储卡的外观。 模块通过使用粘合剂固定在外壳的腔内。 在本发明的每个实施例中，第一和第二盖可移动地附接到壳体，用于选择性地覆盖或暴露存储卡模块的I / O焊盘和测试特征/焊盘。