公开(公告)号：US20110133266A1

公开(公告)日：2011-06-09

申请号：US12629992

申请日：2009-12-03

申请人： Sanh Tang ,  Krishna K. Parat ,  Haitao Liu

发明人： Sanh Tang ,  Krishna K. Parat ,  Haitao Liu

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L27/11548 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11543 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825

摘要： The floating gate of a flash memory may be formed with a flat lower surface facing a substrate and a curved upper surface facing the control gate. In some embodiments, such a device has improved capacitive coupling to the control gate and reduced capacitive coupling to its neighbors.

摘要翻译： 闪存的浮动栅可以形成有面向基板的平坦的下表面和面对控制栅的弯曲的上表面。 在一些实施例中，这种器件具有改善的与控制栅极的电容耦合并且减小与其邻居的电容耦合。

公开(公告)号：US20140252363A1

公开(公告)日：2014-09-11

申请号：US13786925

申请日：2013-03-06

申请人： Haitao Liu ,  Chandra V. Mouli ,  Krishna K. Parat ,  Jie Sun ,  Guangyu Huang

发明人： Haitao Liu ,  Chandra V. Mouli ,  Krishna K. Parat ,  Jie Sun ,  Guangyu Huang

IPC分类号： H01L27/088 ,  H01L21/8239

CPC分类号： H01L27/11582 ,  G11C16/06 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/16 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： A method to fabricate a three dimensional memory structure includes forming an array stack, creating a layer of sacrificial material above the array stack, etching a hole through the layer of sacrificial material and the array stack, creating a pillar of semiconductor material in the hole to form at least two vertically stacked flash memory cells that use the pillar as a common body, removing at least some of the layer of sacrificial material around the pillar to expose a portion of the pillar, and forming a field effect transistor (FET) using the portion of the pillar as the body of the FET.

摘要翻译： 制造三维存储器结构的方法包括形成阵列堆叠，在阵列堆叠上方产生牺牲材料层，蚀刻通过牺牲材料层和阵列堆叠的孔，在孔中产生半导体材料的柱 形成使用该柱作为共同体的至少两个垂直堆叠的闪存单元，去除柱周围的牺牲材料层中的至少一部分以暴露柱的一部分，以及使用该场效应晶体管 柱的一部分作为FET的主体。

公开(公告)号：US08921891B2

公开(公告)日：2014-12-30

申请号：US13592086

申请日：2012-08-22

申请人： Haitao Liu ,  Akira Goda ,  Chandra Mouli ,  Krishna K. Parat

发明人： Haitao Liu ,  Akira Goda ,  Chandra Mouli ,  Krishna K. Parat

IPC分类号： H01L21/336

CPC分类号： H01L29/408 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： Some embodiments include a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to the body, a plurality of access lines adjacent to the body, and a dielectric in a portion of the body between the source/drain and a level corresponding to an end of the plurality of access lines most adjacent to the select gate. The dielectric in the portion of the body does not extend along an entire length of the body. Other embodiments are described and claimed.

摘要翻译： 一些实施例包括具有主体的存储单元串，该主体具有在其中延伸并与源极/漏极接触的通道，与主体相邻的选择栅极，与主体相邻的多个访问线，以及在该部分中的电介质 源极/漏极与对应于与选择栅极最相邻的多条访问线路的端部相对应的电平。 身体部分中的电介质不会沿着身体的整个长度延伸。 描述和要求保护其他实施例。

公开(公告)号：US20140054666A1

公开(公告)日：2014-02-27

申请号：US13592086

申请日：2012-08-22

申请人： Haitao Liu ,  Akira Goda ,  Chandra Mouli ,  Krishna K. Parat

发明人： Haitao Liu ,  Akira Goda ,  Chandra Mouli ,  Krishna K. Parat

IPC分类号： H01L29/788

CPC分类号： H01L29/408 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： Some embodiments include a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to the body, a plurality of access lines adjacent to the body, and a dielectric in a portion of the body between the source/drain and a level corresponding to an end of the plurality of access lines most adjacent to the select gate. The dielectric in the portion of the body does not extend along an entire length of the body. Other embodiments are described and claimed.

摘要翻译： 一些实施例包括具有主体的存储单元串，该主体具有在其中延伸并与源极/漏极接触的通道，与主体相邻的选择栅极，与主体相邻的多个访问线，以及在该部分中的电介质 源极/漏极与对应于与选择栅极最相邻的多条访问线路的端部相对应的电平。 身体部分中的电介质不会沿着身体的整个长度延伸。 描述和要求保护其他实施例。

公开(公告)号：US20220302317A1

公开(公告)日：2022-09-22

申请号：US17301793

申请日：2021-04-14

申请人： Kamal M. Karda ,  Ramanathan Gandhi ,  Hong Li ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Sanh D. Tang ,  Scott E. Sills

发明人： Kamal M. Karda ,  Ramanathan Gandhi ,  Hong Li ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Sanh D. Tang ,  Scott E. Sills

IPC分类号： H01L29/786 ,  H01L29/423 ,  H01L29/10

摘要： A device comprises a vertical transistor. The vertical transistor comprises a semiconductive pillar, at least one gate electrode, a gate dielectric material, and void spaces. The semiconductive pillar comprises a source region, a drain region, and a channel region extending vertically between the source region and the drain region, the channel region comprising a semiconductive material having a band gap greater than 1.65 electronvolts. The at least one gate electrode laterally neighbors the semiconductive pillar. The gate dielectric material is laterally between the semiconductive pillar and the at least one gate electrode. The void spaces are vertically adjacent the gate dielectric material and laterally intervening between the at least one gate electrode and each of the source region and the drain region of the semiconductive pillar. Related electronic systems and methods are also disclosed.

公开(公告)号：US20210066301A1

公开(公告)日：2021-03-04

申请号：US17003037

申请日：2020-08-26

申请人： Kamal M. Karda ,  Karthik Sarpatwari ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

发明人： Kamal M. Karda ,  Karthik Sarpatwari ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

IPC分类号： H01L27/108 ,  G11C11/401

摘要： Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a substrate, a conductive plate located over the substrate to couple a ground connection, a data line located between the substrate and the conductive plate, a memory cell, and a conductive line. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled between the data line and the conductive plate, and a charge storage structure electrically separated from the first region. The second transistor includes a second region electrically coupled to the charge storage structure and the data line. The conductive line is electrically separated from the first and second regions and spans across part of the first region of the first transistor and part of the second region of the second transistor and forming a gate of the first and second transistors.

公开(公告)号：US08717819B2

公开(公告)日：2014-05-06

申请号：US13549743

申请日：2012-07-16

申请人： Seiichi Aritome ,  Haitao Liu ,  Di Li

发明人： Seiichi Aritome ,  Haitao Liu ,  Di Li

IPC分类号： G11C11/34

CPC分类号： G11C16/12

摘要： A programming method and memory structure for preventing punch-through in a short channel source-side select gate structure includes adjusting voltages on the selected and unselected bitlines, and the program, pass, and select gate voltages.

摘要翻译： 用于防止短沟道源侧选择栅极结构中的穿通的编程方法和存储器结构包括调整所选择和未选择的位线上的电压以及编程，通过和选择栅极电压。

公开(公告)号：US20130026471A1

公开(公告)日：2013-01-31

申请号：US13191293

申请日：2011-07-26

申请人： John K. Zahurak ,  Sanh D. Tang ,  Lars P. Heineck ,  Martin C. Roberts ,  Wolfgang Mueller ,  Haitao Liu

发明人： John K. Zahurak ,  Sanh D. Tang ,  Lars P. Heineck ,  Martin C. Roberts ,  Wolfgang Mueller ,  Haitao Liu

IPC分类号： H01L29/786 ,  H01L27/108 ,  H01L21/20 ,  H01L27/08

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L23/528 ,  H01L27/092 ,  H01L27/10802 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/2454 ,  H01L29/36 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7841 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L2924/0002 ,  H01L2924/00

摘要： A circuit structure includes a substrate having an array region and a peripheral region. The substrate in the array and peripheral regions includes insulator material over first semiconductor material, conductive material over the insulator material, and second semiconductor material over the conductive material. The array region includes vertical circuit devices which include the second semiconductor material. The peripheral region includes horizontal circuit devices which include the second semiconductor material. The horizontal circuit devices in the peripheral region individually have a floating body which includes the second semiconductor material. The conductive material in the peripheral region is under and electrically coupled to the second semiconductor material of the floating bodies. Conductive straps in the array region are under the vertical circuit devices. The conductive straps include the conductive material and individually are electrically coupled to a plurality of the vertical circuit devices in the array region. Other implementations are disclosed.

摘要翻译： 电路结构包括具有阵列区域和周边区域的基板。 阵列和外围区域中的衬底包括在第一半导体材料上的绝缘体材料，绝缘体材料上方的导电材料和导电材料上的第二半导体材料。 阵列区域包括包括第二半导体材料的垂直电路器件。 外围区域包括包括第二半导体材料的水平电路器件。 外围区域中的水平电路器件分别具有包括第二半导体材料的浮体。 外围区域中的导电材料在浮体的第二半导体材料的下面并电耦合。 阵列区域中的导电带在垂直电路装置下方。 导电带包括导电材料，并且单独地电耦合到阵列区域中的多个垂直电路器件。 公开了其他实现。

公开(公告)号：US20120275227A1

公开(公告)日：2012-11-01

申请号：US13549743

申请日：2012-07-16

申请人： Seiichi ARITOME ,  Haitao Liu ,  Di Li

发明人： Seiichi ARITOME ,  Haitao Liu ,  Di Li

IPC分类号： G11C16/04

CPC分类号： G11C16/12

摘要： A programming method and memory structure for preventing punch-through in a short channel source-side select gate structure includes adjusting voltages on the selected and unselected bitlines, and the program, pass, and select gate voltages.

摘要翻译： 用于防止短沟道源侧选择栅极结构中的穿通的编程方法和存储器结构包括调整所选择和未选择的位线上的电压以及编程，通过和选择栅极电压。

公开(公告)号：US20110134697A1

公开(公告)日：2011-06-09

申请号：US12630332

申请日：2009-12-03

申请人： Yijie Zhao ,  Akira Goda ,  Jian Li ,  Haitao Liu

发明人： Yijie Zhao ,  Akira Goda ,  Jian Li ,  Haitao Liu

IPC分类号： G11C16/26 ,  G11C16/04 ,  G11C16/34

CPC分类号： G11C11/5642 ,  G11C16/26 ,  G11C16/3418

摘要： Methods for sensing and memory devices are disclosed. One such method for sensing uses a dynamic pass voltage on at least one adjacent memory cell that is adjacent to a selected memory cell for programming. If the adjacent memory cell is not programmed, the pass voltage is reduced on the adjacent memory cell. The adjacent memory cell can be on the drain side, the source side, or both drain and source sides of the selected memory cell.

摘要翻译： 公开了用于感测和存储器件的方法。 用于感测的一种这样的方法在与选定的存储器单元相邻的至少一个相邻存储器单元上使用动态通过电压用于编程。 如果相邻存储单元未编程，则相邻存储单元上的通过电压降低。 相邻的存储单元可以在所选存储单元的漏极侧，源极侧或漏极和源极侧。