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1.发明授权Semiconductor device capable of holding signals independent of the pulse width of an external clock and a computer system including the semiconductor device 失效能够保持独立于外部时钟的脉冲宽度的信号的半导体器件和包括半导体器件的计算机系统
公开(公告)号：US5920510A
公开(公告)日：1999-07-06
申请号：US934202
申请日：1997-09-19
CPC分类号： G11C7/1072 , G11C7/22 , G11C8/06
摘要： A semiconductor device and a computer system, incorporating the same, is capable of capturing an external signal at a high speed and stably operating independent of the duty ratio of a clock signal. An external signal ADD is captured into an address latch 22 by a level latch. The level latch is controlled to a through state at the timing in which the external signal is decided and controlled to a latched state in the decision period of the external signal. A pulse generation circuit controls the timing for switching a latch to the through state to a desired timing by a pulse generation circuit 30 in a chip. According to the above structure, the capture of the external signal ADD can be accelerated because the capture of the signal is determined by the setup timing. Moreover, because a latching period is controlled by the pulse generation circuit in the chip, operations are performed in a stable manner without having to depend upon the pulse width of an external clock CLK.
摘要翻译： 包含该半导体器件和计算机系统的半导体器件和计算机系统能够以与时钟信号的占空比无关地稳定地高速捕获外部信号。 外部信号ADD被电平锁存器捕获到地址锁存器22中。 电平锁存器在外部信号判定时刻的定时被控制为通过状态，并且在外部信号的判定周期中被控制为锁存状态。 脉冲发生电路通过芯片中的脉冲发生电路30控制将锁存器切换到通过状态到期望定时的定时。 根据上述结构，可以加速外部信号ADD的捕获，因为信号的捕获由设置时序确定。 此外，由于锁存周期由芯片中的脉冲发生电路控制，所以以稳定的方式执行操作，而不必依赖于外部时钟CLK的脉冲宽度。
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2.发明授权Logic gate circuit and parallel bit test circuit for semiconductor memory devices, capable of operation at low power source levels 失效用于半导体存储器件的逻辑门电路和并行位测试电路，能够在低电源电平下工作
公开(公告)号：US5646897A
公开(公告)日：1997-07-08
申请号：US426384
申请日：1995-04-21
CPC分类号： G11C29/028 , G11C29/50 , G11C7/1051 , G11C11/41 , G11C2029/5004 , G11C29/34
摘要： A logic circuit is provided for a memory device which can be operated at a high speed with a lower voltage power source level than conventional devices. This logic circuit can be used in a multi-bit test circuit executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, receiving the output of the wired-OR-logic operation by an emitter follower using a bipolar transistor, and outputting an AND signal of the complementary logic signals by a level comparing circuit. A sense amplifier is also provided for executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, raising the level of the output of the wired-OR-logic operation by a level shift circuit having a semiconductor element for applying an inverse bias potential to an input signal, executing the wired-OR-operation of the shifted up output and outputs from other blocks, and receiving and amplifying the output of the wired-OR-logic operation.
摘要翻译： 提供了一种用于存储器件的逻辑电路，其可以以比传统器件更低的电压电源电平在高速下操作。 该逻辑电路可以用于执行来自多个预读取放大器的互补逻辑信号的有线或逻辑运算的多位测试电路，通过射极跟随器接收有线或逻辑运算的输出，使用 双极晶体管，并通过电平比较电路输出互补逻辑信号的“与”信号。 还提供读出放大器，用于执行来自多个预读放大器的互补逻辑信号的有线或逻辑运算，通过具有半导体的电平移位电路提高布线或逻辑运算的输出电平 元件，用于对输入信号施加反向偏置电位，执行移位上升输出的线或运算和其他块的输出，以及接收和放大有线逻辑运算的输出。
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公开(公告)号：US07068551B2
公开(公告)日：2006-06-27
申请号：US11046690
申请日：2005-02-01
IPC分类号： G11C7/00
CPC分类号： G11C5/063 , G11C7/02 , G11C7/1048 , G11C7/18 , G11C11/419 , H01L27/11
摘要： Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
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公开(公告)号：US5761150A
公开(公告)日：1998-06-02
申请号：US651873
申请日：1996-05-21
IPC分类号： G11C11/413 , G06F12/00 , G11C7/10 , G11C8/06 , G11C11/401 , G11C11/407 , G11C11/418 , G11C8/00 , G11C7/00
CPC分类号： G11C8/06 , G11C11/418 , G11C7/1072 , G11C2207/2218
摘要： There is provided a method of controlling an internal address signal of an RAM in which a late-write method is realized on a chip. Two sets of address registers for reading and writing are provided for each address and further a middle register is provided between the two sets of address registers. The middle register is controlled by a signal formed by obtaining the AND result of a clock signal and a write enable signal and the two sets of address registers for reading and writing are controlled only by the clock signal. A selection circuit selects outputs of the two sets of address registers as an input in accordance with the write enable signal to control an internal address.
摘要翻译： 提供了一种控制RAM的内部地址信号的方法，其中在芯片上实现了后期写入方法。 为每个地址提供两组用于读取和写入的地址寄存器，并且还在两组地址寄存器之间提供中间寄存器。 中间寄存器由通过获得时钟信号和写入使能信号的AND结果而形成的信号控制，并且用于读取和写入的两组地址寄存器仅由时钟信号控制。 选择电路根据写使能信号选择两组地址寄存器的输出作为输入，以控制内部地址。
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5.发明授权High-speed semiconductor memory device and data processing system using the same 失效高速半导体存储器件和数据处理系统使用相同
公开(公告)号：US5654931A
公开(公告)日：1997-08-05
申请号：US213531
申请日：1994-03-16
申请人： Akihiro Tamba , Masahiro Iwamura , Yutaka Kobayashi , Kinya Mitsumoto , Tatsumi Yamauchi , Shuko Yamauchi , Takashi Akioka
发明人： Akihiro Tamba , Masahiro Iwamura , Yutaka Kobayashi , Kinya Mitsumoto , Tatsumi Yamauchi , Shuko Yamauchi , Takashi Akioka
CPC分类号： G11C7/22
摘要： A semiconductor integrated circuit device is divided into a plurality of blocks, which are individually equipped with signal generate units such that the signal generate units are distributed in the semiconductor integrated circuit device. The semiconductor integrated circuit device is preferably constructed to generate the pulse signal by the pulse generate units which are provided for the individual blocks, after all initial logic operations on the data and control signals have been taken. Thanks to this construction, an SRAM, for example, can have its write recovery time minimized to 0 so that it can achieve high-speed operations. Moreover, since predecoders are provided for the individual blocks, the wiring line number and area in the chip can be reduced to improve the degree of integration of the semiconductor integrated circuit device. Still moreover, signal delay and skew can be reduced in the chip so that high-speed can be achieved. Another feature is that either the input/output pads of the data into or out of the semiconductor integrated circuit device or their accompanying circuit units are distributed in the semiconductor integrated circuit device. The individual features described above can be used solely or in combination, if necessary, to achieve the above-specified objects.
摘要翻译： 半导体集成电路器件被分成多个块，它们分别配备有信号生成单元，使得信号生成单元分布在半导体集成电路器件中。 优选地，半导体集成电路器件被构造为在对数据和控制信号进行了所有初始逻辑运算之后，通过针对各个块提供的脉冲产生单元产生脉冲信号。 由于这种结构，例如，SRAM可以将其写恢复时间最小化为0，从而可以实现高速操作。 此外，由于为每个块提供预编码器，所以可以减少芯片中的布线数量和面积，以提高半导体集成电路器件的集成度。 此外，芯片中的信号延迟和偏斜可以降低，从而可以实现高速度。 另一个特征是将半导体集成电路器件的数据的输入/输出焊盘或其相应的电路单元分布在半导体集成电路器件中。 如果需要，可以单独地或组合地使用上述各个特征来实现上述目的。
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公开(公告)号：US5631600A
公开(公告)日：1997-05-20
申请号：US361722
申请日：1994-12-23
CPC分类号： G05F3/267
摘要： A constant current generating circuit is provided with a first current generating circuit unit which generates a first current having a positive temperature dependency and includes a pair of first and second bipolar transistors, a first current mirror circuit comprised of a plurality of first MOS transistors which regulates a current density ratio of the currents fed to the first and second bipolar transistors to be constant and derives the first current and a first circuit disposed between the first and second bipolar transistors and the first current mirror circuit for limiting dependency of the currents flowing through the first and second bipolar transistors on a voltage of a power source applied to the first current mirror circuit, a second current generating circuit unit is also provided which generates a second current having as negative temperature dependency and which includes a third bipolar transistor and a second resistor through which the second current is derived. Also, a summing current generating circuit unit is provided which sums the first current and the second current and generates a constant current with substantially no temperature dependency representing the summed current. This summary current generating circuit unit includes a second current mirror circuit comprised of a plurality of second MOS transistors which generates the constant current representing the summed current.
摘要翻译： 恒定电流产生电路具有产生具有正温度依赖性的第一电流并包括一对第一和第二双极晶体管的第一电流产生电路单元，由多个第一MOS晶体管组成的第一电流镜电路，第一MOS晶体管调节 馈送到第一和第二双极晶体管的电流的电流密度比恒定并导出第一电流，以及设置在第一和第二双极晶体管与第一电流镜电路之间的第一电路，用于限制流经 在施加到第一电流镜电路的电源的电压上的第一和第二双极晶体管，还提供产生具有负温度依赖性的第二电流的第二电流产生电路单元，并且包括第三双极晶体管和第二电阻 通过其导出第二电流。 此外，提供了一个求和电流产生电路单元，其将第一电流和第二电流相加，并产生一个恒定电流，基本上没有表示总和电流的温度依赖性。 该汇总电流产生电路单元包括由多个第二MOS晶体管组成的第二电流镜电路，该第二MOS晶体管产生表示总和电流的恒定电流。
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公开(公告)号：US20060158918A1
公开(公告)日：2006-07-20
申请号：US11375060
申请日：2006-03-15
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C7/02 , G11C7/1048 , G11C7/18 , G11C11/419 , H01L27/11
摘要： Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
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公开(公告)号：US5392246A
公开(公告)日：1995-02-21
申请号：US205161
申请日：1994-03-03
IPC分类号： G11C11/413 , G11C29/00 , G11C29/04 , G11C29/24 , G11L7/00
CPC分类号： G11C29/804 , G11C29/24 , G11C29/808
摘要： An area of a semiconductor chip, on which a memory is disposed, is divided into a plurality of memory blocks and redundant memory blocks, each memory block is divided into a plurality of unit arrays of columns for replacing, each redundant memory block is divided into a plurality of unit arrays of redundant columns, a plurality of memory cells are disposed in each unit array of columns for replacing and each unit array of redundant columns, a memory cell group in each unit array of columns for replacing is connected to a word line and a data line, a redundant memory cell group of each unit array of redundant columns is connected to a redundant word line and a redundant data line, a first data selection circuit for controlling data selection with respect to the unit array of redundant columns is disposed in each memory block, a second data selection circuit for controlling data selecting with respect to the unit array group of redundant columns is disposed in each redundant memory block, and a third data selection circuit for selecting and transmitting only data selected either of the data selection circuit is disposed, wherein, if each memory block has no defect, data selected by the first data selection circuit, that is, data selected from the unit array of columns for replacing of each memory block is transmitted as it is by way of the third data selection circuit, if any one of the memory blocks has a defect, data selection with respect to the unit array of columns for replacing that has encountered the defect is inhibited, the unit array of redundant columns of the redundant memory block is instructed in place of the unit array of columns for replacing that has encountered the defect, and data is, by the second data selection circuit, selected from the selected unit array of redundant columns in place of the replacement unit array that has encountered the defect as to transmit the selected data by way of the third data selection circuit.
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公开(公告)号：US06770941B2
公开(公告)日：2004-08-03
申请号：US10002009
申请日：2001-12-05
申请人： Masao Shinozaki , Takashi Akioka , Kinya Mitsumoto
发明人： Masao Shinozaki , Takashi Akioka , Kinya Mitsumoto
IPC分类号： H01L2976
CPC分类号： H01L27/088 , H01L21/823412 , H01L21/823456 , H01L21/823462
摘要： The invention provides a method of producing a semiconductor device conforming to plural supply voltage specifications without increasing the chip size and the production cost, while the device achieves a high-speed performance. The method includes plural processes for forming plural types of MOS transistors supplied with different power supply voltages in correspondence with external power supply voltages, which are comprised of a first process common to the plural types of MOS transistors, a second process following the first process, which is different by each of the plural types of MOS transistors, and a third process following the second process, which is common to the plural types of MOS transistors.
摘要翻译： 本发明提供一种在不增加芯片尺寸和生产成本的情况下制造符合多种电源电压规格的半导体器件的方法，同时器件实现高速性能。 该方法包括多个处理，用于形成与外部电源电压相对应地供应不同电源电压的多种类型的MOS晶体管，这些外部电源电压由多种类型的MOS晶体管共同的第一种处理，第一种处理之后的第二种处理， 这是多种类型的MOS晶体管中的每一种不同的，以及第二种处理之后的第三种处理，这对于多种类型的MOS晶体管是共同的。
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公开(公告)号：US07254068B2
公开(公告)日：2007-08-07
申请号：US11375060
申请日：2006-03-15
IPC分类号： G11C7/00
CPC分类号： G11C5/063 , G11C7/02 , G11C7/1048 , G11C7/18 , G11C11/419 , H01L27/11
摘要： Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
摘要翻译： 为了减少在存储单元读出信号的位线和布置在其上方的信号传输线之间形成的寄生电容。 用于通过互补位线传送从存储单元MC读出的数据的第二互补全局位线布置在存储单元阵列的上方。 每个第二全局位线被布置成使得具有顶点为互补位线之一的部分的中心的三角形，另一个的另一个的部分的中心和第二全局位线的截面的中心位于这些 互补位线是一个等腰三角形。
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