公开(公告)号：US20070184379A1

公开(公告)日：2007-08-09

申请号：US10591345

申请日：2005-03-01

申请人： Shigeo Ashigaki ,  Yoshihiro Kato ,  Yoshihiro Hirota ,  Yusuke Muraki ,  Tetsu Kawasaki ,  Satoru Shimura

发明人： Shigeo Ashigaki ,  Yoshihiro Kato ,  Yoshihiro Hirota ,  Yusuke Muraki ,  Tetsu Kawasaki ,  Satoru Shimura

IPC分类号： G03C1/00

CPC分类号： G03F7/42 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/67051

摘要： A processing method of a substrate includes: a step of forming an Si—C based film and a resist film in turn on an objective film to be etched that has been formed on a substrate; a first etching step of etching the Si—C based film making use of the resist film as a mask; and a second etching step of etching the objective film to be etched making use of the resist film and the Si—C based film as a mask. The processing method further includes a peeling-off step of peeling-off the resist film at a desired timing. The peeling-off step includes a preparing step of preparing an organic solvent as a release agent, and an applying step of applying the organic solvent to the resist film.

摘要翻译： 基板的处理方法包括：依次形成Si-C基膜和抗蚀剂膜的步骤，所述Si-C基膜和抗蚀剂膜依次形成在基板上形成的待蚀刻目标膜上; 蚀刻使用抗蚀剂膜作为掩模的Si-C基膜的第一蚀刻步骤; 以及使用抗蚀剂膜和Si-C基膜作为掩模蚀刻待蚀刻的目标膜的第二蚀刻步骤。 该处理方法还包括在期望的时刻剥离抗蚀剂膜的剥离步骤。 剥离步骤包括制备作为脱模剂的有机溶剂的制备步骤和将有机溶剂施加到抗蚀剂膜的施加步骤。

公开(公告)号：US07897498B2

公开(公告)日：2011-03-01

申请号：US11794325

申请日：2005-11-29

申请人： Glenn Gale ,  Yoshihiro Hirota ,  Yusuke Muraki ,  Genji Nakamura ,  Masato Kushibiki ,  Naoki Shindo ,  Akitaka Shimizu ,  Shigeo Ashigaki ,  Yoshihiro Kato

发明人： Glenn Gale ,  Yoshihiro Hirota ,  Yusuke Muraki ,  Genji Nakamura ,  Masato Kushibiki ,  Naoki Shindo ,  Akitaka Shimizu ,  Shigeo Ashigaki ,  Yoshihiro Kato

IPC分类号： H01L21/336 ,  H01L21/8324 ,  H01L21/76 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/28123 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32139 ,  Y10S438/931

摘要： The present invention is a method of manufacturing a semiconductor device from a layered body including: a semiconductor substrate; a high dielectric film formed on the semiconductor substrate; and an SiC-based film formed on a position upper than the high dielectric film, the SiC-based film having an anti-reflective function and a hardmask function. The present invention comprises a plasma-processing step for plasma-processing the SiC-based film and the high dielectric film to modify the SiC-based film and the high dielectric film by an action of a plasma; and a cleaning step for wet-cleaning the SiC-based film and the high dielectric film modified in the plasma-processing step to collectively remove the SiC-based film and the high dielectric film.

摘要翻译： 本发明是一种从层叠体制造半导体器件的方法，包括：半导体衬底; 形成在所述半导体基板上的高电介质膜; 以及形成在高于高介电膜的位置的SiC基膜，所述SiC基膜具有抗反射功能和硬掩模功能。 本发明包括等离子体处理步骤，用于等离子体处理SiC基膜和高介电膜，以通过等离子体的作用改性SiC基膜和高介电膜; 以及用于湿式清洁在等离子体处理步骤中改性的SiC基膜和高介电膜的清洁步骤，以共同地去除SiC基膜和高介电膜。

公开(公告)号：US20080268655A1

公开(公告)日：2008-10-30

申请号：US11794325

申请日：2005-11-29

申请人： Glenn Gale ,  Yoshihiro Hirota ,  Yusuke Muraki ,  Genji Nakamura ,  Masato Kushibiki ,  Naoki Shindo ,  Akitaka Shimizu ,  Shigeo Ashigaki ,  Yoshihiro Kato

发明人： Glenn Gale ,  Yoshihiro Hirota ,  Yusuke Muraki ,  Genji Nakamura ,  Masato Kushibiki ,  Naoki Shindo ,  Akitaka Shimizu ,  Shigeo Ashigaki ,  Yoshihiro Kato

IPC分类号： H01L21/469 ,  H01L21/00

CPC分类号： H01L21/28123 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32139 ,  Y10S438/931

摘要： The present invention is a method of manufacturing a semiconductor device from a layered body including: a semiconductor substrate; a high dielectric film formed on the semiconductor substrate; and an SiC-based film formed on a position upper than the high dielectric film, the SiC-based film having an anti-reflective function and a hardmask function. The present invention comprises a plasma-processing step for plasma-processing the SiC-based film and the high dielectric film to modify the SiC-based film and the high dielectric film by an action of a plasma; and a cleaning step for wet-cleaning the SiC-based film and the high dielectric film modified in the plasma-processing step to collectively remove the SiC-based film and the high dielectric film.

摘要翻译： 本发明是一种从层叠体制造半导体器件的方法，包括：半导体衬底; 形成在所述半导体基板上的高电介质膜; 以及形成在高于高介电膜的位置的SiC基膜，所述SiC基膜具有抗反射功能和硬掩模功能。 本发明包括等离子体处理步骤，用于等离子体处理SiC基膜和高介电膜，以通过等离子体的作用改性SiC基膜和高介电膜; 以及用于湿式清洁在等离子体处理步骤中改性的SiC基膜和高介电膜的清洁步骤，以共同地去除SiC基膜和高介电膜。

公开(公告)号：US08241982B2

公开(公告)日：2012-08-14

申请号：US12942057

申请日：2010-11-09

申请人： Yoshihiro Hirota ,  Yoshihiro Sato ,  Nobuo Okumura

发明人： Yoshihiro Hirota ,  Yoshihiro Sato ,  Nobuo Okumura

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/0214 ,  H01L21/02332 ,  H01L21/28273 ,  H01L21/31111 ,  H01L21/3144 ,  H01L21/3211 ,  H01L21/76232 ,  H01L29/42336 ,  H01L29/7881

摘要： A plasma nitriding process is followed by a selective etching process which removes a silicon oxynitride film formed on surfaces of both an element separation film and an insulation film while leaving a silicon nitride film formed on an electrode layer. The selective etching process removes the silicon oxynitride film formed on the surfaces of the element separation film and the insulation film.

摘要翻译： 等离子体氮化处理之后是选择性蚀刻工艺，其除去在元件分离膜和绝缘膜的表面上形成的氮氧化硅膜，同时留下形成在电极层上的氮化硅膜。 选择性蚀刻工艺除去在元件分离膜和绝缘膜的表面上形成的氧氮化硅膜。

公开(公告)号：US20070181928A1

公开(公告)日：2007-08-09

申请号：US11508141

申请日：2006-08-23

申请人： Yoshiki Yamanishi ,  Muneo Harada ,  Takahiro Kitano ,  Tatsuzo Kawaguchi ,  Yoshihiro Hirota ,  Kinji Yamada ,  Tomotaka Shinoda ,  Katsuya Okumura ,  Shuichi Kawano

发明人： Yoshiki Yamanishi ,  Muneo Harada ,  Takahiro Kitano ,  Tatsuzo Kawaguchi ,  Yoshihiro Hirota ,  Kinji Yamada ,  Tomotaka Shinoda ,  Katsuya Okumura ,  Shuichi Kawano

IPC分类号： H01L29/94

CPC分类号： H01L23/50 ,  H01G4/228 ,  H01G4/33 ,  H01L23/481 ,  H01L24/81 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01056 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K1/162 ,  H05K3/002 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/10378

摘要： A capacitor having a high quality and a manufacturing method of the same are provided. A capacitor has a lower electrode formed on an oxide film, a dielectric layer formed on the lower electrode, an upper electrode formed so as to face the lower electrode with the dielectric layer between, and an upper electrode formed so as to cover the upper electrode, an opening portion of the upper electrode and an opening portion of the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to pattern the dielectric layer by using the upper electrode as a mask, and provide a capacitor having a high-quality dielectric layer by preventing impurity diffusion into the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to prevent the dielectric layer from being exposed to etching liquid, liquid developer, etc.

摘要翻译： 提供了具有高质量的电容器及其制造方法。 电容器具有形成在氧化膜上的下电极，形成在下电极上的电介质层，形成为与电极之间介电层相对的下电极的上电极和形成为覆盖上电极的上电极 ，上电极的开口部分和电介质层的开口部分。 通过在电介质层上形成上电极，可以通过使用上电极作为掩模对电介质层进行图案化，并且通过防止杂质扩散到电介质层中来提供具有高质量电介质层的电容器。 通过在电介质层上形成上部电极，可以防止电介质层暴露于蚀刻液体，液体显影剂等

公开(公告)号：US20070126041A1

公开(公告)日：2007-06-07

申请号：US11508204

申请日：2006-08-23

申请人： Tomotaka Shinoda ,  Kinji Yamada ,  Takahiro Kitano ,  Yoshiki Yamanishi ,  Muneo Harada ,  Tatsuzo Kawaguchi ,  Yoshihiro Hirota ,  Katsuya Okumura ,  Shuichi Kawano

发明人： Tomotaka Shinoda ,  Kinji Yamada ,  Takahiro Kitano ,  Yoshiki Yamanishi ,  Muneo Harada ,  Tatsuzo Kawaguchi ,  Yoshihiro Hirota ,  Katsuya Okumura ,  Shuichi Kawano

IPC分类号： H01L29/94 ,  H01L21/00

CPC分类号： H01L28/65 ,  H01L27/11507 ,  H01L28/55 ,  Y10T29/435

摘要： A dielectric film capacitor includes a lower electrode having an opening and formed of a material including platinum, a dielectric film provided over the lower electrode and including an oxide having an ABOx crystal structure, and an upper electrode provided over the dielectric film. The planar area of the lower electrode is 50% or more of the area of a formation region of the dielectric film. A dielectric film capacitor includes a lower electrode formed of a material including platinum and having a thickness of 10 to 100 nm, a dielectric film provided over the lower electrode and including an oxide having an ABOx crystal structure, and an upper electrode provided over the dielectric film.

摘要翻译： 电介质膜电容器包括具有开口并由包括铂的材料形成的下电极，设置在下电极上并包括具有ABOx晶体结构的氧化物的电介质膜和设置在电介质膜上的上电极。 下部电极的平面面积为电介质膜的形成区域的面积的50％以上。 电介质膜电容器包括由包括铂的材料形成的厚度为10至100nm的下电极，设置在下电极上并包括具有ABOx晶体结构的氧化物的电介质膜，以及设置在电介质上的上电极 电影。

公开(公告)号：US07161360B2

公开(公告)日：2007-01-09

申请号：US11002070

申请日：2004-12-03

申请人： Yoshihiro Hirota ,  Toshiyuki Matsumoto ,  Tatsuo Hiroshima

发明人： Yoshihiro Hirota ,  Toshiyuki Matsumoto ,  Tatsuo Hiroshima

IPC分类号： G01R27/26

CPC分类号： H03K17/955 ,  G01D5/2405 ,  H03K2217/960765

摘要： An electrostatic capacitance sensor, includes an electrostatic capacitance detector, an operational amplifier in which a feedback impedance circuit is connected between an output terminal and an inverse input terminal of the operational amplifier, a signal line connected between the inverse input terminal of the operational amplifier and the electrostatic capacitance detector, an alternating-current signal generator connected to a non-inverse input terminal of the operational amplifier, and a shield for shielding at least a portion of the signal line, the shield being connected to the non-inverse input terminal of the operational amplifier and the alternating-current signal generator. The electrostatic capacitance detector includes a detecting electrode and a shield electrode. The detecting electrode includes a detector-detecting electrode for detecting an object to be detected and an electrode introducer-detecting electrode for introducing an electrode to the detector-detecting electrode. The shield electrode is connected to the shield. At least a portion of the electrode introducer-detecting electrode is shielded by the shield electrode.

摘要翻译： 一种静电电容传感器，包括静电电容检测器，其中反馈阻抗电路连接在运算放大器的输出端和反相输入端之间的运算放大器，连接在运算放大器的反相输入端和 所述静电电容检测器，连接到所述运算放大器的非反相输入端的交流信号发生器和用于屏蔽所述信号线的至少一部分的屏蔽，所述屏蔽连接到所述运算放大器的非反相输入端 运算放大器和交流信号发生器。 静电电容检测器包括检测电极和屏蔽电极。 检测电极包括用于检测待检测物体的检测器检测电极和用于将电极引入检测器检测电极的电极引导器检测电极。 屏蔽电极连接到屏蔽。 电极引导器检测电极的至少一部分被屏蔽电极屏蔽。

公开(公告)号：US07026504B2

公开(公告)日：2006-04-11

申请号：US10470126

申请日：2001-01-26

申请人： Masao Yamaguchi ,  Hiromasa Yamamoto ,  Hideki Kikuchi ,  Yoshihiro Hirota

发明人： Masao Yamaguchi ,  Hiromasa Yamamoto ,  Hideki Kikuchi ,  Yoshihiro Hirota

IPC分类号： C07C69/52

CPC分类号： C07C67/60 ,  C07C2603/74 ,  G03F7/0397 ,  C07C69/54 ,  C07C69/013

摘要： There is provided a method for obtaining a high-purity alkyladamantyl ester from an alkyladamantyl ester composition containing a large quantity of alkyladamantyl halide obtained by, for example, alkylating raw material 2-adamantanone obtained through oxidation of adamantane by use of an organic metal reagent and then causing an acid halide to react with the resulting product, efficiently by a simple process. To an alkyladamantyl ester composition containing an alkyladamantyl halide such as 2-chloro-2-methyladamantane in an amount of larger than 0.5 parts by weight based on 100 parts by weight of alkyladamantyl ester such as 2-methyl-2-adamantyl methacrylate, a mixed solution of, for example, methanol and a sodium hydroxide aqueous solution is added. By bringing the alkali compound into contact with the alkyladamantyl halide in a homogeneous system so as to convert the halide into a compound which produces no acid when heated, the amount of the alkyladamantyl halide in the composition is reduced to 0.5 parts by weight or less based on 100 parts by weight of the alkyladamantyl ester, after which distillation is carried out.

摘要翻译： 提供了一种从含有大量烷基金刚烷基卤化物的烷基金刚烷基酯组合物中获得高纯度烷基金刚烷基酯的方法，所述烷基金刚烷基酯通过使用有机金属试剂将金刚烷氧化而得到的原料2-金刚烷烷化， 然后通过简单的方法使酰基卤与所得产物反应。 对于基于100重量份的烷基金刚烷基酯如甲基丙烯酸2-甲基-2-金刚烷基酯，含有烷基金刚烷基卤化物如2-氯-2-甲基金刚烷的量大于0.5重量份的烷基金刚烷基酯组合物，混合 加入例如甲醇和氢氧化钠水溶液的溶液。 通过使碱性化合物与均匀体系中的烷基金刚烷基卤化物接触，以便将卤化物转化为加热时不产生酸的化合物，组合物中烷基金刚烷基卤化物的量降低至基于0.5重量份或更少 在100重量份的烷基金刚烷基酯上进行蒸馏。

公开(公告)号：US06348809B1

公开(公告)日：2002-02-19

申请号：US09371546

申请日：1999-08-10

申请人： Yoshihiro Hirota ,  Toshiyuki Matsumoto

发明人： Yoshihiro Hirota ,  Toshiyuki Matsumoto

IPC分类号： G01R3126

CPC分类号： G01R27/2605

摘要： There is provided a probing and measurement system for measuring a capacitance value of a capacitance to be measured, by removing any influence made by a parasitic capacitance and a fluctuation thereof within a shield box 11. The probing and measurement system comprises a prober 1, a signal line having one end to be in contact with a sample to be measured, a shield line surrounding the signal line, and a capacitance measurement circuit 6. The capacitance measurement circuit 6 comprises an operational amplifier 61 having an inverting input terminal connected to the other end of the signal line and a non-inverting input terminal connected to the shield line, wherein an imaginary short state exists between the inverting input terminal and the non-inverting input terminal, and wherein a signal having a value corresponding to an electrostatic capacitance of the sample to be measured is outputted when an AC signal is applied to the non-inverting input terminal. Conductive portions of the shield box 11, conductive portions of a stand 13, a surface of the stand which contacts with the sample to be measured, and the shield line are placed at the same electric potential.

摘要翻译： 提供了一种用于测量待测电容的电容值的探测和测量系统，通过消除由屏蔽盒11内的寄生电容及其波动引起的任何影响。探测和测量系统包括探测器1， 信号线，其一端与要测量的样本接触，围绕信号线的屏蔽线以及电容测量电路6.电容测量电路6包括运算放大器61，其具有与另一个连接的反相输入端 信号线的端部和连接到屏蔽线的非反相输入端子，其中在反相输入端子和非反相输入端子之间存在虚拟短路状态，并且其中具有对应于静电电容值的信号 当将AC信号施加到非反相输入端时，输出要测量的样本。 屏蔽盒11的导电部分，支架13的导电部分，与待测样品接触的支架的表面和屏蔽线放置在相同的电位。

公开(公告)号：US08258571B2

公开(公告)日：2012-09-04

申请号：US12665534

申请日：2008-06-20

申请人： Tetsuo Endoh ,  Masayuki Kohno ,  Tatsuo Nishita ,  Minoru Honda ,  Toshio Nakanishi ,  Yoshihiro Hirota

发明人： Tetsuo Endoh ,  Masayuki Kohno ,  Tatsuo Nishita ,  Minoru Honda ,  Toshio Nakanishi ,  Yoshihiro Hirota

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  C23C16/308 ,  C23C16/345 ,  G11C11/5628 ,  G11C16/0466 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/7926

摘要： The invention provides a MOS semiconductor memory device that achieves excellent data retention characteristics while also achieving high-speed data write performance, low-power operation performance, and high reliability. A MOS semiconductor memory device 601 includes a first insulating film 111 and fifth insulating film 115 having large bandgaps 111a and 115a, a third insulating film 113 having the smallest bandgap 113a, and a second insulating film 112 and fourth insulating film 114 interposed between the third insulating film 113 and the first and fifth insulating films 111 and 115, respectively, and having intermediate bandgaps 112a and 114a.

摘要翻译： 本发明提供一种实现优异的数据保持特性的MOS半导体存储器件，同时还实现了高速数据写入性能，低功率操作性能和高可靠性。 MOS半导体存储器件601包括具有较大带隙111a和115a的第一绝缘膜111和第五绝缘膜115，具有最小带隙113a的第三绝缘膜113和介于第三绝缘膜113之间的第二绝缘膜112和第四绝缘膜114。 绝缘膜113和第一和第五绝缘膜111和115，并具有中间带隙112a和114a。