公开(公告)号：US6163062A

公开(公告)日：2000-12-19

申请号：US71158

申请日：1998-05-04

申请人： Shigeru Shiratake ,  Hideki Genjo ,  Yasuhiro Ido ,  Atsushi Hachisuka ,  Koji Taniguchi

发明人： Shigeru Shiratake ,  Hideki Genjo ,  Yasuhiro Ido ,  Atsushi Hachisuka ,  Koji Taniguchi

IPC分类号： H01L21/82 ,  H01L21/768 ,  H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5258 ,  H01L21/76888 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a plurality of fuse members (1a, 1b) composed of a metal that can be cut by laser light (4), disposed over a semiconductor substrate (5). The length L of the fuse members (1a, 1b) is smaller than a value obtained by subtracting an alignment error .alpha. of the laser light (4) from a spot diameter D of the laser light (4), i.e., the value (D-.alpha.). The fuse members (1a, 1b) are spaced a distance l larger than a value obtained by adding the alignment error .alpha. to the half of the spot diameter D, i.e., the value (D/2+.alpha.).

摘要翻译： 一种半导体器件具有多个由可由激光（4）切割的金属构成的保险丝构件（1a，1b），设置在半导体衬底（5）上。 保险丝构件（1a，1b）的长度L小于从激光（4）的光斑直径D减去激光（4）的取向误差α所得到的值，即值（D - α ）。 保险丝构件（1a，1b）的间隔距离l大于通过将对准误差α加到光斑直径D的一半，即值（D / 2 +α）而获得的值。

公开(公告)号：US06765251B2

公开(公告)日：2004-07-20

申请号：US09227935

申请日：1999-01-11

申请人： Eiji Hasunuma ,  Hideki Genjo ,  Shigeru Shiratake ,  Atsushi Hachisuka ,  Koji Taniguchi

发明人： Eiji Hasunuma ,  Hideki Genjo ,  Shigeru Shiratake ,  Atsushi Hachisuka ,  Koji Taniguchi

IPC分类号： H01L27108

CPC分类号： H01L27/10852 ,  H01L21/28568 ,  H01L21/76814 ,  H01L21/76831 ,  H01L27/10808

摘要： In the semiconductor device, in order to meet the demand of reduced diameter of a contact hole along with the miniaturization of the semiconductor device, an anti-HF side wall film which is not etched by a hydrofluoric acid, formed of an isolating film such as nitride film, is provided on the side wall of contact hole. Further, a second impurity region which is connected to one of the pair of n type source/drain regions and a first impurity region reaching a p type isolation region are provided in silicon substrate 1 near the lower end of contact hole. Because of this structure, it becomes possible to prevent expansion of the diameter for forming the interconnection layer, as desired in the miniaturized semiconductor device, and therefore a semiconductor device and manufacturing method thereof which stabilize operation characteristic of the semiconductor device can be provided.

摘要翻译： 在半导体装置中，为了满足半导体装置的小型化使接触孔的直径减小的要求，没有被氢氟酸腐蚀的抗HF侧壁膜由隔离膜形成，例如 氮化物膜设置在接触孔的侧壁上。 此外，在接触孔下端附近的硅衬底1中设置有连接到一对n型源极/漏极区域中的一个和到达p型隔离区域的第一杂质区域的第二杂质区域。 由于这种结构，可以根据小型半导体器件的需要防止用于形成互连层的直径的膨胀，因此可以提供稳定半导体器件的操作特性的半导体器件及其制造方法。

公开(公告)号：US5153689A

公开(公告)日：1992-10-06

申请号：US404528

申请日：1989-09-08

申请人： Yoshinori Okumura ,  Takayuki Matsukawa ,  Ikuo Ogoh ,  Masao Nagatomo ,  Hideki Genjo ,  Atsushi Hachisuka

发明人： Yoshinori Okumura ,  Takayuki Matsukawa ,  Ikuo Ogoh ,  Masao Nagatomo ,  Hideki Genjo ,  Atsushi Hachisuka

IPC分类号： H01L21/3205 ,  H01L21/8242 ,  H01L23/52 ,  H01L23/532 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10808 ,  H01L23/53257 ,  H01L2924/0002

摘要： A memory cell of a semiconductor memory device comprises one MOS transistor (3) and one stacked capacitor (4). One of the source/drain regions (8a, 8b) of the MOS transistor is connected to a bit line (2a, 2b). The bit line is formed from a contact portion to the source/drain regions of the MOS transistor to a portion above the stacked capacitor. The bit line is formed of a metal having high melting point, a silicide of a metal having high melting point or a polycide. Since this material has low reflectance against exposing light, the precision in patterning the interconnection is improved.

摘要翻译： 半导体存储器件的存储单元包括一个MOS晶体管（3）和一个堆叠电容器（4）。 MOS晶体管的源极/漏极区域（8a，8b）之一连接到位线（2a，2b）。 位线由MOS晶体管的源极/漏极区域到层叠电容器上方的部分的接触部分形成。 位线由具有高熔点的金属，具有高熔点的金属的硅化物或多晶硅化物形成。 由于该材料对于曝光具有低的反射率，因此提高了互连图形化的精度。

公开(公告)号：US5077238A

公开(公告)日：1991-12-31

申请号：US353892

申请日：1989-05-18

申请人： Atsuhiro Fujii ,  Toshihiko Minami ,  Hideki Genjo

发明人： Atsuhiro Fujii ,  Toshihiko Minami ,  Hideki Genjo

IPC分类号： H01L21/3105 ,  H01L21/311 ,  H01L21/312 ,  H01L21/768

CPC分类号： H01L21/31111 ,  H01L21/31055 ,  H01L21/312 ,  H01L21/76819 ,  H01L21/76804 ,  Y10S148/133 ,  Y10S438/98

摘要： A method of manufacturing a semiconductor device in which an element is flattened by improving a technique of forming an interlayer insulating film. A thick insulating film having a film thickness necessary for a convexo-concave pattern to be flattened is deposited on a semiconductor substrate comprising the convexo-concave pattern of an element, a wiring and the like. Then, the thick insulating film is etched until it becomes a predetermined film thickness to form an interlayer insulating film having a predetermined film thickness from said thick insulating film. At this time, since acid and water are attached on the surface of the interlayer insulating film, a new film is formed on the surface of the interlayer insulating film to cover this water and acid. Then, a resist pattern having a desired configuration is formed on this new film. A contact hole is formed on the interlayer insulating film using this resist pattern. Thereafter, a wiring pattern electrically connected to the element is formed on the interlayer insulating film through the contact hole. According to this method, since the acid and water attached on the interlayer insulating film are covered with the new film, the adhesion between the interlayer insulating film and the resist is improved. As a result, the contact hole can be opened reliably, whereby the element is surely connected to the wiring pattern and a semiconductor device can be provided with high reliability.

摘要翻译： 通过改进形成层间绝缘膜的技术来制造半导体器件的方法，其中元件被平坦化。 在包含元件的凸凹图形，布线等的半导体衬底上沉积具有要平坦化的凹凸图案所需的膜厚度的厚绝缘膜。 然后，对厚的绝缘膜进行蚀刻，直至其变为预定的膜厚度，以从所述厚绝缘膜形成具有预定膜厚度的层间绝缘膜。 此时，由于酸和水附着在层间绝缘膜的表面上，所以在层间绝缘膜的表面上形成新的膜以覆盖该水和酸。 然后，在该新膜上形成具有所需结构的抗蚀剂图案。 使用该抗蚀剂图案在层间绝缘膜上形成接触孔。 此后，通过接触孔在层间绝缘膜上形成与元件电连接的布线图案。 根据该方法，由于附着在层间绝缘膜上的酸和水被新的膜覆盖，所以层间绝缘膜和抗蚀剂之间的粘合性提高。 结果，可以可靠地打开接触孔，从而元件可靠地连接到布线图案，并且可以提供高可靠性的半导体器件。

公开(公告)号：US5132774A

公开(公告)日：1992-07-21

申请号：US618284

申请日：1990-11-28

申请人： Masazumi Matsuura ,  Hideo Kotani ,  Atsuhiro Fujii ,  Shigeo Nagao ,  Hideki Genjo

发明人： Masazumi Matsuura ,  Hideo Kotani ,  Atsuhiro Fujii ,  Shigeo Nagao ,  Hideki Genjo

IPC分类号： H01L21/02 ,  H01L21/316 ,  H01L21/768

CPC分类号： H01L28/40 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76834

摘要： The method of forming an interlayer insulating film insulating first and second layers of conductor patterns in a semiconductor device includes the steps of preparing a reaction gas including at least ozone and silicon alkoxide, wherein the ratio of ozone with respect to silicon alkoxide is adjusted to be not less than 5 within the reaction gas, and forming an insulating film by CVD reacting the reaction gas at atmospheric pressure at the temperature of 350.degree. C.-450.degree. C., whereupon the interlayer insulating film includes at least the insulating film formed by atmospheric pressure CVD reaction.

摘要翻译： 在半导体器件中形成绝缘第一和第二导体图案层的层间绝缘膜的方法包括以下步骤：制备至少包括臭氧和硅氧烷的反应气体，其中臭氧与烷氧基硅的比例调节为 在反应气体内不少于5个，并通过CVD在大气压下在350℃-450℃下使反应气体反应形成绝缘膜，于是层间绝缘膜至少包括由 大气压CVD反应。

公开(公告)号：US5250468A

公开(公告)日：1993-10-05

申请号：US857141

申请日：1992-03-25

申请人： Masazumi Matsuura ,  Hideo Kotani ,  Atsuhiro Fujii ,  Shigeo Nagao ,  Hideki Genjo

发明人： Masazumi Matsuura ,  Hideo Kotani ,  Atsuhiro Fujii ,  Shigeo Nagao ,  Hideki Genjo

IPC分类号： H01L21/02 ,  H01L21/316 ,  H01L21/768 ,  H01L21/441

CPC分类号： H01L28/40 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/02214 ,  H01L21/02271 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834

摘要： The method of forming an interlayer insulating film insulating first and second layers of conductor patterns in a semiconductor device includes the steps of preparing a reaction gas including at least ozone and silicon alkoxide, wherein the ratio of ozone with respect to silicon alkoxide is adjusted to be not less than 5 within the reaction gas, and forming an insulating film by CVD reacting the reaction gas at atmospheric pressure at the temperature of 350.degree. C.- 450.degree. C., whereupon the interlayer insulating film includes at least the insulating film formed by atmospheric pressure CVD reaction.

摘要翻译： 在半导体器件中形成绝缘第一和第二导体图案层的层间绝缘膜的方法包括以下步骤：制备至少包括臭氧和硅氧烷的反应气体，其中臭氧与烷氧基硅的比例调节为 在反应气体内不少于5个，并通过在350℃-450℃的温度下在大气压下使反应气体进行CVD反应形成绝缘膜，由此层间绝缘膜至少包括由 大气压CVD反应。

公开(公告)号：US5231041A

公开(公告)日：1993-07-27

申请号：US819206

申请日：1992-01-10

申请人： Hideaki Arima ,  Yoshinori Okumura ,  Hideki Genjo ,  Ikuo Ogoh ,  Kohjiroh Yuzuriha ,  Yuichi Nakashima

发明人： Hideaki Arima ,  Yoshinori Okumura ,  Hideki Genjo ,  Ikuo Ogoh ,  Kohjiroh Yuzuriha ,  Yuichi Nakashima

IPC分类号： H01L21/8247 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L29/42332 ,  H01L29/7886

摘要： A 1-transistor type flash EEPROM is disclosed. The memory cell in the EEPROM includes a control gate formed on a silicon substrate with an insulating layer disposed between them, and a floating gate formed to extend over the upper face and one side face of the control electrode with an insulating layer disposed between them. Drain and source regions are created in the silicon substrate on the opposite sides of the control gate. The area in the silicon substrate under the control gate between the drain and source regions defines a channel region. In the EEPROM, an application of high-level voltage to the control gate and the drain region produces hot electrons in the vicinity of the opposite ends of the drain region which are driven into the floating gate across the insulating layer, causing the floating gate to store data-representing charge. The flash EEPROM has uniform characteristics among memory cells and reduced cell area for improved miniaturization.

摘要翻译： 公开了1晶体管型快闪EEPROM。 EEPROM中的存储单元包括形成在硅衬底上的控制栅极，绝缘层设置在它们之间，并且浮置栅极形成为在控制电极的上表面和一个侧面之间设置绝缘层。 在控制栅极的相对侧的硅衬底中产生漏极和源极区。 在漏极和源极区域之间的控制栅极下方的硅衬底中的区域限定沟道区域。 在EEPROM中，向控制栅极和漏极区域施加高电平电压在漏极区域的相对端附近产生热电子，这些电极驱动跨越绝缘层的浮动栅极，从而使浮动栅极 存储数据代表费用。 闪存EEPROM在存储单元之间具有均匀的特性，并且减小了单元面积以改善小型化。

公开(公告)号：US5101250A

公开(公告)日：1992-03-31

申请号：US630439

申请日：1990-12-20

申请人： Hideaki Arima ,  Yoshinori Okumura ,  Hideki Genjo ,  Ikuo Ogoh ,  Kohjiroh Yuzuriha ,  Yuichi Nakashima

发明人： Hideaki Arima ,  Yoshinori Okumura ,  Hideki Genjo ,  Ikuo Ogoh ,  Kohjiroh Yuzuriha ,  Yuichi Nakashima

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L29/42332 ,  H01L29/7886

摘要： A 1-transistor type flash EEPROM is disclosed. The memory cell in the EEPROM includes a control gate formed on a silicon substrate with an insulating layer disposed between them, and a floating gate formed to extend over the upper face and one side face of the control electrode with an insulating layers disposed between them. Drain and source regions are created in the silicon substrate on the opposite sides of the control gate. The area in the silicon substrate under the control gate between the drain and source regions defines a channel region. In the EEPROM, an application of high-level voltage to the control gate and the drain region produces hot electrons in the vicinity of the opposite ends of the drain region which are driven into the floating gate across the insulating layer, causing the floating gate to store data-representing charge. The flash EEPROM has uniform characteristics among memory cells and reduced cell area for improved miniaturization.

摘要翻译： 公开了1晶体管型快闪EEPROM。 EEPROM中的存储单元包括形成在硅衬底上的控制栅极，绝缘层位于它们之间，浮栅形成为在控制电极的上表面和一个侧面之间设置绝缘层。 在控制栅极的相对侧的硅衬底中产生漏极和源极区。 在漏极和源极区域之间的控制栅极下方的硅衬底中的区域限定沟道区域。 在EEPROM中，向控制栅极和漏极区域施加高电平电压在漏极区域的相对端附近产生热电子，这些电极驱动跨越绝缘层的浮动栅极，从而使浮动栅极 存储数据代表费用。 闪存EEPROM在存储单元之间具有均匀的特性，并且减小了单元面积以改善小型化。