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    Wafer level transparent packaging
    1.
    发明申请
    Wafer level transparent packaging 审中-公开
    晶圆级透明包装

    公开(公告)号：US20050095750A1

    公开(公告)日：2005-05-05

    申请号：US10948214

    申请日：2004-09-24

    申请人： Jian-Wen Lo ,  Shin-Hua Chao ,  Chia-Yi Hu

    发明人： Jian-Wen Lo ,  Shin-Hua Chao ,  Chia-Yi Hu

    IPC分类号： H01L21/56 ,  H01L21/60 ,  H01L21/78 ,  H01L23/31 ,  H01L21/50 ,  H01L21/301 ,  H01L21/44 ,  H01L21/46 ,  H01L21/48

    CPC分类号： H01L23/3171 ,  H01L21/56 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/18 ,  H01L24/82 ,  H01L2224/18 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/3512

    摘要： A process for manufacturing transparent semiconductor packages is disclosed. A wafer having an active surface and a back surface is provided. A plurality of first redistribution lines are formed on the active surface of the wafer to connect the bonding pads of the chips. A transparent polymer is formed over the active surface of the wafer to cover the first redistribution lines. A plurality of first grooves are formed corresponding to the scribe lines and in the back surface of the wafer. Preferably, a back coating is then formed over the back surface to fill the first grooves. Next, a plurality of second grooves are formed corresponding to the first grooves and through the back coating such that the first redistribution lines have exposed portions. A plurality of second redistribution lines on the back coating can extend to the exposed portions of the corresponding first redistribution lines for connecting solder balls on the back surface.

    摘要翻译： 公开了一种制造透明半导体封装的工艺。 提供具有活性表面和背面的晶片。 在晶片的有源表面上形成多个第一再分配线以连接芯片的焊盘。 在晶片的有效表面上形成透明聚合物以覆盖第一再分配线。 多个第一槽形成对应于划痕线和晶片的后表面。 优选地，在后表面上形成背涂以填充第一凹槽。 接下来，对应于第一凹槽和通过后涂层形成多个第二凹槽，使得第一再分布线具有暴露部分。 后涂层上的多个第二再分配线可以延伸到相应的第一再分配线的暴露部分，用于连接后表面上的焊球。

    Multi-chip package structure
    2.
    发明授权
    Multi-chip package structure 有权
    多芯片封装结构

    公开(公告)号：US07151317B2

    公开(公告)日：2006-12-19

    申请号：US10904404

    申请日：2004-11-09

    申请人： Shin-Hua Chao ,  Jian-Wen Lo

    发明人： Shin-Hua Chao ,  Jian-Wen Lo

    IPC分类号： H01L23/48

    CPC分类号： H01L25/0652 ,  H01L24/14 ,  H01L24/17 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17505 ,  H01L2224/81986 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599

    摘要： A multi-chip package structure comprising a first chip, a patterned lamination layer, a plurality of first bumps, a second chip and second bumps is provided. The first chip has a first active surface. The patterned lamination layer is disposed on a portion area of the first active surface. The first chip has a plurality of first bonding pads disposed on the first active surface exposed by the patterned lamination layer and the patterned lamination layer has a plurality of second bonding pads disposed thereon. The second chip has a second active surface and the first bumps are disposed on the second active surface. The second chip is electrically connected to the first bonding pads through the first bumps. The second bumps are disposed on the second bonding pads. Moreover, the multi-chip package structure further comprises a component disposed on the first chip and electrically connects to the first bonding pads.

    摘要翻译： 提供了包括第一芯片，图案化层压层，多个第一凸块，第二芯片和第二凸块的多芯片封装结构。 第一芯片具有第一活性表面。 图案化层压层设置在第一活性表面的一部分区域上。 第一芯片具有多个第一接合焊盘，其设置在由图案化层压层暴露的第一有源表面上，并且图案化层叠层具有设置在其上的多个第二接合焊盘。 第二芯片具有第二有源表面，并且第一突起设置在第二有源表面上。 第二芯片通过第一凸块电连接到第一焊盘。 第二凸块设置在第二接合焊盘上。 此外，多芯片封装结构还包括设置在第一芯片上并与第一焊盘电连接的部件。

    MULTI-CHIP PACKAGE STRUCTURE
    3.
    发明申请
    MULTI-CHIP PACKAGE STRUCTURE 有权
    多芯片包装结构

    公开(公告)号：US20050199991A1

    公开(公告)日：2005-09-15

    申请号：US10904404

    申请日：2004-11-09

    申请人： Shin-Hua Chao ,  Jian-Wen Lo

    发明人： Shin-Hua Chao ,  Jian-Wen Lo

    IPC分类号： H01L23/48

    CPC分类号： H01L25/0652 ,  H01L24/14 ,  H01L24/17 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17505 ,  H01L2224/81986 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599

    摘要： A multi-chip package structure comprising a first chip, a patterned lamination layer, a plurality of first bumps, a second chip and second bumps is provided. The first chip has a first active surface. The patterned lamination layer is disposed on a portion area of the first active surface. The first chip has a plurality of first bonding pads disposed on the first active surface exposed by the patterned lamination layer and the patterned lamination layer has a plurality of second bonding pads disposed thereon. The second chip has a second active surface and the first bumps are disposed on the second active surface. The second chip is electrically connected to the first bonding pads through the first bumps. The second bumps are disposed on the second bonding pads. Moreover, the multi-chip package structure further comprises a component disposed on the first chip and electrically connects to the first bonding pads.

    摘要翻译： 提供了包括第一芯片，图案化层压层，多个第一凸块，第二芯片和第二凸块的多芯片封装结构。 第一芯片具有第一活性表面。 图案化层压层设置在第一活性表面的一部分区域上。 第一芯片具有多个第一接合焊盘，其设置在由图案化层压层暴露的第一有源表面上，并且图案化层叠层具有设置在其上的多个第二接合焊盘。 第二芯片具有第二有源表面，并且第一突起设置在第二有源表面上。 第二芯片通过第一凸块电连接到第一焊盘。 第二凸块设置在第二接合焊盘上。 此外，多芯片封装结构还包括设置在第一芯片上并与第一焊盘电连接的部件。

    Three-dimensional package and method of making the same
    5.
    发明授权
    Three-dimensional package and method of making the same 有权
    三维包装及其制作方法

    公开(公告)号：US07642132B2

    公开(公告)日：2010-01-05

    申请号：US11584546

    申请日：2006-10-23

    申请人： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

    发明人： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

    IPC分类号： H01L21/44

    CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/05099

    摘要： The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a semiconductor body; (b) forming at least one blind hole in the semiconductor body; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) patterning the conductive layer; (f) removing a part of the lower surface of the semiconductor body and a part of the isolation layer, so as to expose a part of the conductive layer; (g) forming a solder on the lower end of the conductive layer; (h) stacking a plurality of the semiconductor bodies, and performing a reflow process; and (i) cutting the stacked semiconductor bodies, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer and the solder thereon are “inserted” into the space formed by the conductive layer of the lower semiconductor body, so as to enhance the joining between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.

    摘要翻译： 本发明涉及三维包装及其制造方法。 该方法包括：（a）提供半导体本体; （b）在半导体本体中形成至少一个盲孔; （c）在盲孔的侧壁上形成隔离层; （d）在隔离层上形成导电层; （e）图案化导电层; （f）去除所述半导体主体的下表面的一部分和所述隔离层的一部分，以暴露所述导电层的一部分; （g）在导电层的下端形成焊料; （h）堆叠多个半导体体，进行回流处理; 和（i）切割堆叠的半导体本体，以便形成多个三维封装。 因此，导电层的下端和其上的焊料被“插入”到由下半导体本体的导电层形成的空间中，以便增强导电层和焊料之间的接合，并且有效地减少 加入后三维包装的整体高度。

    Three-dimensional package and method of making the same
    9.
    发明申请
    Three-dimensional package and method of making the same 有权
    三维包装及其制作方法

    公开(公告)号：US20070172984A1

    公开(公告)日：2007-07-26

    申请号：US11645040

    申请日：2006-12-26

    申请人： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

    发明人： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

    IPC分类号： H01L21/00

    CPC分类号： H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a wafer; (b) forming at least one blind hole in the wafer; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) forming a dry film on the conductive layer; (f) filling the blind hole with a solder; (g) removing the dry film; (h) patterning the conductive layer; (i) removing a part of the lower surface of the wafer and a part of the isolation layer, so as to expose a part of the conductive layer; (j) stacking a plurality of the wafers, and performing a reflow process; and (k) cutting the stacked wafers, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer is inserted into the solder of the lower wafer, so as to enhance the joint between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.

    摘要翻译： 本发明涉及三维包装及其制造方法。 该方法包括：（a）提供晶片; （b）在所述晶片中形成至少一个盲孔; （c）在盲孔的侧壁上形成隔离层; （d）在隔离层上形成导电层; （e）在导电层上形成干膜; （f）用焊料填充盲孔; （g）去除干膜; （h）图案化导电层; （i）去除所述晶片的下表面的一部分和所述隔离层的一部分，以暴露所述导电层的一部分; （j）堆叠多个晶片，并进行回流处理; 和（k）切割堆叠的晶片，以便形成多个三维封装。 因此，导电层的下端插入下晶片的焊料中，以增强导电层和焊料之间的接合，并且有效地降低了连接后三维封装的整体高度。

    Three-dimensional package and method of making the same
    10.
    发明申请
    Three-dimensional package and method of making the same 有权
    三维包装及其制作方法

    公开(公告)号：US20070172982A1

    公开(公告)日：2007-07-26

    申请号：US11584546

    申请日：2006-10-23

    申请人： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

    发明人： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

    IPC分类号： H01L21/00

    CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/05099

    摘要： The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a semiconductor body; (b) forming at least one blind hole in the semiconductor body; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) patterning the conductive layer; (f) removing a part of the lower surface of the semiconductor body and a part of the isolation layer, so as to expose a part of the conductive layer; (g) forming a solder on the lower end of the conductive layer; (h) stacking a plurality of the semiconductor bodies, and performing a reflow process; and (i) cutting the stacked semiconductor bodies, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer and the solder thereon are “inserted” into the space formed by the conductive layer of the lower semiconductor body, so as to enhance the joining between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.

    摘要翻译： 本发明涉及三维包装及其制造方法。 该方法包括：（a）提供半导体本体; （b）在半导体本体中形成至少一个盲孔; （c）在盲孔的侧壁上形成隔离层; （d）在隔离层上形成导电层; （e）图案化导电层; （f）去除所述半导体主体的下表面的一部分和所述隔离层的一部分，以暴露所述导电层的一部分; （g）在导电层的下端形成焊料; （h）堆叠多个半导体体，进行回流处理; 和（i）切割堆叠的半导体本体，以便形成多个三维封装。 因此，导电层的下端和其上的焊料被“插入”到由下半导体本体的导电层形成的空间中，以便增强导电层和焊料之间的接合，并且有效地减少 加入后三维包装的整体高度。