公开(公告)号：US20120221616A1

公开(公告)日：2012-08-30

申请号：US13428150

申请日：2012-03-23

申请人： Shinichi YASUDA ,  Kazutaka IKEGAMI

发明人： Shinichi YASUDA ,  Kazutaka IKEGAMI

IPC分类号： G06F7/58

CPC分类号： H03K3/84 ,  G06F7/588

摘要： According to one embodiment, a random number generation circuit includes an oscillation circuit and a holding circuit. The oscillation circuit has an amplifier array and a high-noise circuit. Amplifiers are connected in series in the amplifier array, and the amplifier array has a terminal between neighboring amplifiers. The high-noise circuit is inserted between other neighboring amplifiers in the amplifier array, and the high-noise circuit generates noise required to generate jitter in an oscillation signal from the amplifier array. The holding circuit outputs, as a random number, the oscillation signal held according to a clock signal.

摘要翻译： 根据一个实施例，随机数生成电路包括振荡电路和保持电路。 振荡电路具有放大器阵列和高噪声电路。 放大器在放大器阵列中串联连接，放大器阵列在相邻放大器之间具有一个端子。 高噪声电路插入在放大器阵列中的其它相邻放大器之间，高噪声电路产生在放大器阵列的振荡信号中产生抖动所需的噪声。 保持电路作为随机数输出根据时钟信号保持的振荡信号。

公开(公告)号：US20090157780A1

公开(公告)日：2009-06-18

申请号：US12122503

申请日：2008-05-16

申请人： Shinichi YASUDA ,  Shinobu Fujita

发明人： Shinichi YASUDA ,  Shinobu Fujita

IPC分类号： G06F1/02

CPC分类号： G06F7/58

摘要： A random number generating circuit receives as input a first digital random number signal generated at a first generating rate and produces as output a second digital random number signal having a second generating rate that is twice as high as the first generating rate. A semiconductor integrated circuit, an IC card and an information terminal device comprising the random number circuit is provided.

摘要翻译： 随机数产生电路接收以第一产生速率产生的第一数字随机数信号作为输出，产生第二数字随机数信号，该第二数字随机数信号的第二发生速率是第一发生速率的两倍。 提供了包括随机数电路的半导体集成电路，IC卡和信息终端装置。

公开(公告)号：US20140035618A1

公开(公告)日：2014-02-06

申请号：US13613701

申请日：2012-09-13

申请人： Kosuke TATSUMURA ,  Masato ODA ,  Atsuhiro KINOSHITA ,  Koichiro ZAITSU ,  Mari MATSUMOTO ,  Shinichi YASUDA

发明人： Kosuke TATSUMURA ,  Masato ODA ,  Atsuhiro KINOSHITA ,  Koichiro ZAITSU ,  Mari MATSUMOTO ,  Shinichi YASUDA

IPC分类号： H03K19/177

CPC分类号： H03K19/17728 ,  G11C15/04 ,  G11C15/046 ,  H03K19/17712

摘要： A circuit according to embodiments includes: a plurality of bit-string comparators each of which includes a plurality of single-bit comparators each of which includes first and second input terminals, first and second match-determination terminals, and a memory storing data and inverted data in a pair, the first input terminal being connected to a respective search line, the second input terminal being connected to an inverted search line being paired with the respective search line, and a matching line connecting the first and second match-determination terminals of the single-bit comparators; a pre-charge transistor of which source is connected to a supply voltage line; a common matching line connected to a drain of the pre-charge transistor and the matching lines of the bit-string comparators; and an output inverter of which input is connected to the common matching line.

摘要翻译： 根据实施例的电路包括：多个比特串比较器，每个比特串包括多个单比特比较器，每个单比特比较器包括第一和第二输入端，第一和第二匹配确定终端，以及存储数据并反转的存储器 成对的数据，第一输入端子连接到相应的搜索线，第二输入端子连接到与相应搜索线配对的反向搜索线，以及匹配线，连接第一和第二匹配确定端子 单比特比较器; 其源极连接到电源电压线的预充电晶体管; 连接到预充电晶体管的漏极和位串比较器的匹配线的公共匹配线; 以及输入反相器，其输入连接到公共匹配线。

公开(公告)号：US20130215670A1

公开(公告)日：2013-08-22

申请号：US13719775

申请日：2012-12-19

申请人： Masato ODA ,  Koichiro ZAITSU ,  Kiwamu SAKUMA ,  Shinichi YASUDA ,  Kohei OIKAWA

发明人： Masato ODA ,  Koichiro ZAITSU ,  Kiwamu SAKUMA ,  Shinichi YASUDA ,  Kohei OIKAWA

IPC分类号： G11C11/40

CPC分类号： G11C11/40 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0002 ,  G11C16/0441 ,  H03K19/1776

摘要： A memory circuit according to an embodiment includes: a plurality of memory cells each having one pair of first and second nonvolatile memory circuits, each of the first and second nonvolatile memory circuits in each memory cell being capable of making a transition between a high resistance state and a low resistance state, and in a state in which one memory cell in the plurality of memory cells has information stored therein, one of the first and second nonvolatile memory circuits in the one memory cell being in a high resistance state whereas the other being in a low resistance state.

摘要翻译： 根据实施例的存储器电路包括：多个存储单元，每个存储单元具有一对第一和第二非易失性存储器电路，每个存储单元中的每个第一和第二非易失性存储器电路能够在高电阻状态 和低电阻状态，并且在多个存储单元中的一个存储单元存储有信息的状态下，一个存储单元中的第一和第二非易失性存储器电路之一处于高电阻状态，而另一个存储单元 处于低电阻状态。

公开(公告)号：US20120230105A1

公开(公告)日：2012-09-13

申请号：US13232550

申请日：2011-09-14

申请人： Shinichi YASUDA ,  Masato Oda ,  Kumiko Nomura ,  Keiko Abe ,  Shinobu Fujita

发明人： Shinichi YASUDA ,  Masato Oda ,  Kumiko Nomura ,  Keiko Abe ,  Shinobu Fujita

IPC分类号： G11C16/04 ,  G11C5/06

CPC分类号： H03K19/17728 ,  G11C13/0002 ,  G11C16/0466 ,  H03K19/17768

摘要： In one embodiment, a semiconductor integrated circuit has memory cells. Each of the memory cells has non-volatile memories and switching elements. The non-volatile memories and switching elements are connected in series between a first power source and a second power source. Output wirings of at least two of the memory cells are connected to each other. Input wirings are connected with control gates of the switching elements included in each of the at least two memory cells. A plurality of the switching elements included in one of the at least two of the memory cells is turned off, when an input signal or an inverted signal is inputted. Further, another plurality of the switching elements included in another one of the at least two of memory cells other than the one of the memory cells is turned on, when the input signal or the inverted signal is inputted.

摘要翻译： 在一个实施例中，半导体集成电路具有存储单元。 每个存储单元具有非易失性存储器和开关元件。 非易失性存储器和开关元件串联连接在第一电源和第二电源之间。 至少两个存储单元的输出布线彼此连接。 输入布线与包括在至少两个存储单元中的每一个中的开关元件的控制栅极连接。 当输入信号或反相信号被输入时，包括在至少两个存储单元之一中的多个开关元件被断开。 此外，当输入信号或反相信号被输入时，包括在存储单元之外的至少两个存储单元中的另一个存储单元中的另外多个开关元件导通。

公开(公告)号：US20130307054A1

公开(公告)日：2013-11-21

申请号：US13606292

申请日：2012-09-07

申请人： Shinichi YASUDA ,  Kosuke Tatsumura ,  Mari Matsumoto ,  Koichiro Zaitsu ,  Masato Oda ,  Atsuhiro Kinoshita ,  Daisuke Hagishima ,  Yoshifumi Nishi ,  Takahiro Kurita ,  Shinobu Fujita

发明人： Shinichi YASUDA ,  Kosuke Tatsumura ,  Mari Matsumoto ,  Koichiro Zaitsu ,  Masato Oda ,  Atsuhiro Kinoshita ,  Daisuke Hagishima ,  Yoshifumi Nishi ,  Takahiro Kurita ,  Shinobu Fujita

IPC分类号： H01L27/105

CPC分类号： G11C16/10 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/11526 ,  H01L27/11573 ,  H01L29/7881 ,  H01L29/792

摘要： One embodiment provides a semiconductor integrated circuit, including: a substrate; a plurality of nonvolatile memory portions formed in the substrate, each including a first nonvolatile memory and a second nonvolatile memory; and a plurality of logic transistor portions formed in the substrate, each including at least one of logic transistor, wherein the logic transistors include: a first transistor which is directly connected to drains of the first and second nonvolatile memories at its gate; and a second transistor which is not directly connected to the drains of the first and second nonvolatile memories, and wherein a bottom surface of the gate of each of the logic transistors sandwiching the first and second nonvolatile memories is lower in height from a top surface of the substrate than a bottom surface of the control gate of each of the first and second nonvolatile memories.

摘要翻译： 一个实施例提供一种半导体集成电路，包括：基板; 形成在所述基板中的多个非易失性存储部，每个包括第一非易失性存储器和第二非易失性存储器; 以及形成在所述衬底中的多个逻辑晶体管部分，每个逻辑晶体管部分包括逻辑晶体管中的至少一个，其中所述逻辑晶体管包括：第一晶体管，其第一和第二非易失性存储器的栅极直接连接到第一晶体管; 以及第二晶体管，其不直接连接到第一和第二非易失性存储器的漏极，并且其中夹着第一和第二非易失性存储器的每个逻辑晶体管的栅极的底表面的高度与 所述基板比所述第一和第二非易失性存储器中的每一个的所述控制栅极的底表面。

公开(公告)号：US20130258782A1

公开(公告)日：2013-10-03

申请号：US13603666

申请日：2012-09-05

申请人： Kosuke TATSUMURA ,  Masato ODA ,  Koichiro ZAITSU ,  Atsushi KAWASUMI ,  Mari MATSUMOTO ,  Shinichi YASUDA

发明人： Kosuke TATSUMURA ,  Masato ODA ,  Koichiro ZAITSU ,  Atsushi KAWASUMI ,  Mari MATSUMOTO ,  Shinichi YASUDA

IPC分类号： G11C16/06

CPC分类号： G11C16/06 ,  G11C7/06 ,  G11C16/26

摘要： According to one embodiment, a configuration memory includes first and second data lines, a first memory string which comprises at least first and second nonvolatile memory transistors which are connected in series between a common node and the first data line, a second memory string which comprises at least third and fourth nonvolatile memory transistors which are connected in series between the common node and the second data line, and a flip-flop circuit which comprises a first data holding node connected to the common node and a second data holding node connected to a configuration data output node.

摘要翻译： 根据一个实施例，配置存储器包括第一和第二数据线，第一存储器串，其包括串联连接在公共节点和第一数据线之间的至少第一和第二非易失性存储器晶体管，第二存储器串包括 在公共节点和第二数据线之间串联连接的至少第三和第四非易失性存储器晶体管，以及包括连接到公共节点的第一数据保持节点和连接到公共节点的第二数据保持节点的触发器电路 配置数据输出节点。

公开(公告)号：US20120243336A1

公开(公告)日：2012-09-27

申请号：US13240087

申请日：2011-09-22

申请人： Yoshifumi NISHI ,  Daisuke HAGISHIMA ,  Shinichi YASUDA ,  Tetsufumi TANAMOTO ,  Takahiro KURITA ,  Atsuhiro KINOSHITA ,  Shinobu FUJITA

发明人： Yoshifumi NISHI ,  Daisuke HAGISHIMA ,  Shinichi YASUDA ,  Tetsufumi TANAMOTO ,  Takahiro KURITA ,  Atsuhiro KINOSHITA ,  Shinobu FUJITA

IPC分类号： G11C16/10 ,  H01L29/792

CPC分类号： H01L27/11568 ,  G11C16/0458 ,  G11C16/10 ,  H01L27/11573 ,  H01L27/11803

摘要： An aspect of the present embodiment, there is provided a nonvolatile programmable logic switch including a first memory cell transistor, a second memory cell transistor, a pass transistor and a first substrate electrode applying a substrate voltage to the pass transistor, wherein a writing voltage is applied to the first wiring, a first voltage is applied to one of a second wiring and a third wiring and a second voltage which is lower than the first voltage is applied to the other of the second wiring and the third wiring, and the first substrate voltage which is higher than the second voltage and lower than the first voltage is applied to a well of the pass transistor, when data is written into the first memory cell transistor or the second memory cell transistor.

摘要翻译： 本实施例的一个方面提供了一种非易失性可编程逻辑开关，包括第一存储单元晶体管，第二存储单元晶体管，传输晶体管和向该通过晶体管施加衬底电压的第一衬底电极，其中写入电压为 施加到第一布线，第一电压施加到第二布线和第三布线中的一个，并且低于第一电压的第二电压施加到第二布线和第三布线中的另一布线，第一基板 当数据被写入第一存储单元晶体管或第二存储单元晶体管时，高于第二电压并低于第一电压的电压被施加到传输晶体管的阱。

公开(公告)号：US20090249141A1

公开(公告)日：2009-10-01

申请号：US12367379

申请日：2009-02-06

申请人： Shinichi YASUDA

发明人： Shinichi YASUDA

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/31725 ,  G01R31/31727

摘要： A semiconductor integrated circuit includes a flipflop holding and outputting input data according to a clock, the flipflop having: an input end to which data is input; an output end from which data is output; a first logic gate connected between the input end and the output end, the first logic gate operating according to the clock; a second logic gate connected between the first logic gate and the output end, the second logic gate operating according to the clock; and a buffer circuit. An input of the buffer circuit is connected to a node between the first logic gate and the input end. An output of the buffer circuit is connected to a node in an output side of the first logic gate. The buffer circuit transitions according to an enable signal from a high impedance state to a state in which a signal can be transmitted.

摘要翻译： 一种半导体集成电路包括触发器，其保持并根据时钟输出输入数据，所述触发器具有：输入数据的输入端; 输出数据的输出端; 连接在输入端和输出端之间的第一逻辑门，第一逻辑门根据时钟工作; 连接在第一逻辑门和输出端之间的第二逻辑门，第二逻辑门根据时钟工作; 和缓冲电路。 缓冲电路的输入连接到第一逻辑门和输入端之间的节点。 缓冲电路的输出连接到第一逻辑门的输出侧的节点。 缓冲电路根据从高阻抗状态的使能信号转换到可以发送信号的状态。