公开(公告)号：US08610246B2

公开(公告)日：2013-12-17

申请号：US13084074

申请日：2011-04-11

申请人： Shinji Yoshihara ,  Kazushi Asami ,  Yasuhiro Kitamura ,  Junji Oohara

发明人： Shinji Yoshihara ,  Kazushi Asami ,  Yasuhiro Kitamura ,  Junji Oohara

IPC分类号： H01L29/00

CPC分类号： H01L21/6835 ,  H01F5/003 ,  H01F41/041 ,  H01F41/046 ,  H01L2924/0002 ,  H05K1/165 ,  H05K2201/09672 ,  H01L2924/00

摘要： In a manufacturing method for a semiconductor device having a coil layer part on a substrate, two support substrates each having a flat surface are prepared, and a component member is formed on the flat surface of each of the support substrates. The component member includes a wiring portion having a predetermined pattern and an insulation film surrounding the wiring portion. The wiring portion is provided with a connecting portion exposing from the insulation film. A coil layer part is formed by opposing and bonding the component members formed on the support substrates to each other while applying pressure in a condition where the flat surfaces of the support substrates are parallel to each other. A coil is formed in the coil layer part by connecting the wiring portions through the connecting portions.

摘要翻译： 在具有在基板上具有线圈层部分的半导体器件的制造方法中，准备了具有平坦表面的两个支撑基板，并且在每个支撑基板的平坦表面上形成有部件。 该部件包括具有预定图案的布线部分和围绕布线部分的绝缘膜。 布线部分设置有从绝缘膜露出的连接部分。 线圈层部分通过在支撑基板的平坦表面彼此平行的状态下相对地并且将形成在支撑基板上的部件彼此相对并粘合而形成，同时施加压力。 通过连接部分连接布线部分，在线圈层部分中形成线圈。

公开(公告)号：US20110248380A1

公开(公告)日：2011-10-13

申请号：US13084074

申请日：2011-04-11

申请人： Shinji YOSHIHARA ,  Kazushi Asami ,  Yasuhiro Kitamura ,  Junji Oohara

发明人： Shinji YOSHIHARA ,  Kazushi Asami ,  Yasuhiro Kitamura ,  Junji Oohara

IPC分类号： H01L29/86 ,  H01L21/20

CPC分类号： H01L21/6835 ,  H01F5/003 ,  H01F41/041 ,  H01F41/046 ,  H01L2924/0002 ,  H05K1/165 ,  H05K2201/09672 ,  H01L2924/00

摘要： In a manufacturing method for a semiconductor device having a coil layer part on a substrate, two support substrates each having a flat surface are prepared, and a component member is formed on the flat surface of each of the support substrates. The component member includes a wiring portion having a predetermined pattern and an insulation film surrounding the wiring portion. The wiring portion is provided with a connecting portion exposing from the insulation film. A coil layer part is formed by opposing and bonding the component members formed on the support substrates to each other while applying pressure in a condition where the flat surfaces of the support substrates are parallel to each other. A coil is formed in the coil layer part by connecting the wiring portions through the connecting portions.

摘要翻译： 在具有在基板上具有线圈层部分的半导体器件的制造方法中，准备了具有平坦表面的两个支撑基板，并且在每个支撑基板的平坦表面上形成有部件。 该部件包括具有预定图案的布线部分和围绕布线部分的绝缘膜。 布线部分设置有从绝缘膜露出的连接部分。 线圈层部分通过在支撑基板的平坦表面彼此平行的状态下相对地并且将形成在支撑基板上的部件彼此相对并粘合而形成，同时施加压力。 通过连接部分连接布线部分，在线圈层部分中形成线圈。

公开(公告)号：US20110244687A1

公开(公告)日：2011-10-06

申请号：US13073173

申请日：2011-03-28

申请人： Junji OOHARA ,  Kazushi Asami

发明人： Junji OOHARA ,  Kazushi Asami

IPC分类号： H01L21/306

CPC分类号： H01L21/30655 ,  H01J37/321 ,  H01J37/32972 ,  H01L22/26

摘要： In a process for forming trenches having M different widths in a substrate, a passivation step and an etching step are alternately performed. The passivation step includes depositing a passivation layer on a bottom of the trenches by converting gas introduced in a chamber into plasma. The etching step includes removing the passivation layer on the bottom of the trenches and applying reactive ion etching to the bottom to increase a depth of the trenches. The etching step further includes setting energy for the reactive ion etching to a predetermined value when the passivation layer on the bottom of the trench having the Nth smallest width is removed. The value allows the etching amount of the trench having the Nth smallest width to be equal to or greater than the etching amount of the trench having the (N+1)th smallest width.

摘要翻译： 在用于形成在衬底中具有M个不同宽度的沟槽的工艺中，交替执行钝化步骤和蚀刻步骤。 钝化步骤包括通过将在腔室中引入的气体转化为等离子体来在沟槽的底部沉积钝化层。 蚀刻步骤包括去除沟槽底部的钝化层并向底部施加反应离子蚀刻以增加沟槽的深度。 当去除具有第N个最小宽度的沟槽底部的钝化层时，蚀刻步骤还包括将反应离子蚀刻的能量设定为预定值。 该值允许具有第N个最小宽度的沟槽的蚀刻量等于或大于具有（N + 1）个最小宽度的沟槽的蚀刻量。

公开(公告)号：US20050054153A1

公开(公告)日：2005-03-10

申请号：US10936539

申请日：2004-09-09

申请人： Kazushi Asami ,  Junji Oohara ,  Hiroshi Muto ,  Kazuhiko Sugiura ,  Tsuyoshi Fukada ,  Yukihiro Takeuchi

发明人： Kazushi Asami ,  Junji Oohara ,  Hiroshi Muto ,  Kazuhiko Sugiura ,  Tsuyoshi Fukada ,  Yukihiro Takeuchi

IPC分类号： B81C1/00 ,  H01L21/306 ,  H01L29/80 ,  H05K3/06

CPC分类号： B81C1/00619 ,  B81C2201/0112

摘要： A method for manufacturing a semiconductor device having a movable portion includes the steps of: forming a trench on a semiconductor layer so that the trench reaches an insulation layer; and forming a movable portion by etching a sidewall of the trench so that the semiconductor layer is separated from the insulation layer. The steps of forming the trench and forming the movable portion are performed by a reactive ion etching method. The insulation layer disposed on the bottom of the trench is prevented from charging positively in the step of forming the trench. The insulation layer disposed on the bottom of the trench is charged positively in the step of forming the movable portion.

摘要翻译： 一种制造具有可移动部分的半导体器件的方法包括以下步骤：在半导体层上形成沟槽，使得沟槽到达绝缘层; 以及通过蚀刻沟槽的侧壁形成可动部分，使得半导体层与绝缘层分离。 通过反应离子蚀刻方法进行形成沟槽并形成可动部的步骤。 在形成沟槽的步骤中，防止设置在沟槽底部的绝缘层被正面地充电。 设置在沟槽底部的绝缘层在形成可移动部分的步骤中被正向地充电。

公开(公告)号：US08461052B2

公开(公告)日：2013-06-11

申请号：US13073173

申请日：2011-03-28

申请人： Junji Oohara ,  Kazushi Asami

发明人： Junji Oohara ,  Kazushi Asami

IPC分类号： H01L21/461

CPC分类号： H01L21/30655 ,  H01J37/321 ,  H01J37/32972 ,  H01L22/26

摘要： In a process for forming trenches having M different widths in a substrate, a passivation step and an etching step are alternately performed. The passivation step includes depositing a passivation layer on a bottom of the trenches by converting gas introduced in a chamber into plasma. The etching step includes removing the passivation layer on the bottom of the trenches and applying reactive ion etching to the bottom to increase a depth of the trenches. The etching step further includes setting energy for the reactive ion etching to a predetermined value when the passivation layer on the bottom of the trench having the Nth smallest width is removed. The value allows the etching amount of the trench having the Nth smallest width to be equal to or greater than the etching amount of the trench having the (N+1)th smallest width.

摘要翻译： 在用于形成在衬底中具有M个不同宽度的沟槽的工艺中，交替执行钝化步骤和蚀刻步骤。 钝化步骤包括通过将在腔室中引入的气体转化为等离子体来在沟槽的底部沉积钝化层。 蚀刻步骤包括去除沟槽底部的钝化层并向底部施加反应离子蚀刻以增加沟槽的深度。 当去除具有第N个最小宽度的沟槽底部的钝化层时，蚀刻步骤还包括将反应离子蚀刻的能量设定为预定值。 该值允许具有第N个最小宽度的沟槽的蚀刻量等于或大于具有（N + 1）个最小宽度的沟槽的蚀刻量。

公开(公告)号：US07214625B2

公开(公告)日：2007-05-08

申请号：US10936539

申请日：2004-09-09

申请人： Kazushi Asami ,  Junji Oohara ,  Hiroshi Muto ,  Kazuhiko Sugiura ,  Tsuyoshi Fukada ,  Yukihiro Takeuchi

发明人： Kazushi Asami ,  Junji Oohara ,  Hiroshi Muto ,  Kazuhiko Sugiura ,  Tsuyoshi Fukada ,  Yukihiro Takeuchi

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L29/82

CPC分类号： B81C1/00619 ,  B81C2201/0112

摘要： A method for manufacturing a semiconductor device having a movable portion includes the steps of: forming a trench on a semiconductor layer so that the trench reaches an insulation layer; and forming a movable portion by etching a sidewall of the trench so that the semiconductor layer is separated from the insulation layer. The steps of forming the trench and forming the movable portion are performed by a reactive ion etching method. The insulation layer disposed on the bottom of the trench is prevented from charging positively in the step of forming the trench. The insulation layer disposed on the bottom of the trench is charged positively in the step of forming the movable portion.

摘要翻译： 一种制造具有可移动部分的半导体器件的方法包括以下步骤：在半导体层上形成沟槽，使得沟槽到达绝缘层; 以及通过蚀刻沟槽的侧壁形成可动部分，使得半导体层与绝缘层分离。 通过反应离子蚀刻方法进行形成沟槽并形成可动部的步骤。 在形成沟槽的步骤中，防止设置在沟槽底部的绝缘层被正面地充电。 设置在沟槽底部的绝缘层在形成可移动部分的步骤中被正向地充电。

公开(公告)号：US06287885B1

公开(公告)日：2001-09-11

申请号：US09306381

申请日：1999-05-06

申请人： Hiroshi Muto ,  Tsuyoshi Fukada ,  Masakazu Terada ,  Hiroshige Sugito ,  Masakazu Kanosue ,  Shinji Yoshihara ,  Shoji Ozoe ,  Seiji Fujino ,  Minekazu Sakai ,  Minoru Murata ,  Yukihiro Takeuchi ,  Seiki Aoyama ,  Toshio Yamamoto ,  Kazushi Asami

发明人： Hiroshi Muto ,  Tsuyoshi Fukada ,  Masakazu Terada ,  Hiroshige Sugito ,  Masakazu Kanosue ,  Shinji Yoshihara ,  Shoji Ozoe ,  Seiji Fujino ,  Minekazu Sakai ,  Minoru Murata ,  Yukihiro Takeuchi ,  Seiki Aoyama ,  Toshio Yamamoto ,  Kazushi Asami

IPC分类号： H01L21302

CPC分类号： B81C1/00936 ,  B81B3/0005 ,  B81B2201/0235 ,  B81B2201/025 ,  B81B2203/0136 ,  B81B2203/033 ,  B81B2203/04 ,  B81C2201/0132 ,  B81C2201/053 ,  B81C2201/112 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814 ,  G01P2015/084

摘要： In a method for manufacturing a semiconductor acceleration sensor, a movable portion including a mass portion and movable electrodes is formed in a single crystal silicon thin film provided on a silicon wafer through an insulation film by etching both the single crystal silicon thin film and the silicon wafer. In this case, the movable portion is finally defined at a movable portion defining step that is carried out in a vapor phase atmosphere. Accordingly, the movable portion is prevented from sticking to other regions due to etchant during the manufacture thereof.

公开(公告)号：US08471363B2

公开(公告)日：2013-06-25

申请号：US13246065

申请日：2011-09-27

申请人： Kazushi Asami ,  Yasuhiro Kitamura

发明人： Kazushi Asami ,  Yasuhiro Kitamura

IPC分类号： H01L21/02 ,  H01L21/8222

CPC分类号： H01L28/91 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/642 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a substrate, a first single conductor, a single insulator, and a second single conductor. The substrate includes first and second regions located adjacent to each other. The first region has blind holes, each of which has an opening on a front surface of the substrate. The second region has a through hole penetrating the substrate. A width of each blind hole is less than a width of the through hole. The first single conductor is formed on the front surface of the substrate in such a manner that an inner surface of each blind hole and an inner surface of the through hole are covered with the first single conductor. The single insulator is formed on the first single conductor. The second single conductor is formed on the single insulator and electrically insulated form the first single conductor.

摘要翻译： 半导体器件包括衬底，第一单导体，单绝缘体和第二单导体。 衬底包括彼此相邻定位的第一和第二区域。 第一区域具有盲孔，每个盲孔在基板的前表面上具有开口。 第二区域具有穿透基板的通孔。 每个盲孔的宽度小于通孔的宽度。 第一单导体形成在基板的前表面上，使得每个盲孔的内表面和通孔的内表面被第一单导体覆盖。 单个绝缘体形成在第一单个导体上。 第二单导体形成在单个绝缘体上并且电绝缘形成第一单导体。

公开(公告)号：US20120080772A1

公开(公告)日：2012-04-05

申请号：US13246065

申请日：2011-09-27

申请人： Kazushi Asami ,  Yasuhiro Kitamura

发明人： Kazushi Asami ,  Yasuhiro Kitamura

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/91 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/642 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a substrate, a first single conductor, a single insulator, and a second single conductor. The substrate includes first and second regions located adjacent to each other. The first region has blind holes, each of which has an opening on a front surface of the substrate. The second region has a through hole penetrating the substrate. A width of each blind hole is less than a width of the through hole. The first single conductor is formed on the front surface of the substrate in such a manner that an inner surface of each blind hole and an inner surface of the through hole are covered with the first single conductor. The single insulator is formed on the first single conductor. The second single conductor is formed on the single insulator and electrically insulated form the first single conductor.

摘要翻译： 半导体器件包括衬底，第一单导体，单绝缘体和第二单导体。 衬底包括彼此相邻定位的第一和第二区域。 第一区域具有盲孔，每个盲孔在基板的前表面上具有开口。 第二区域具有穿透基板的通孔。 每个盲孔的宽度小于通孔的宽度。 第一单导体形成在基板的前表面上，使得每个盲孔的内表面和通孔的内表面被第一单导体覆盖。 单个绝缘体形成在第一单个导体上。 第二单导体形成在单个绝缘体上并且电绝缘形成第一单导体。

公开(公告)号：US08256289B2

公开(公告)日：2012-09-04

申请号：US12923971

申请日：2010-10-19

申请人： Kazuhiko Kano ,  Akihiko Teshigahara ,  Kazuki Arakawa ,  Kazushi Asami

发明人： Kazuhiko Kano ,  Akihiko Teshigahara ,  Kazuki Arakawa ,  Kazushi Asami

IPC分类号： G01P9/04

CPC分类号： G01C19/5698

摘要： An angular rate sensor comprises a piezoelectric film having a first and a second surfaces forming an x-y plane and utilizes a perturbation mass coherently vibrating elastic acoustic waves on which a Coriolis force acts when the angular rate sensor undergoes a rotary motion about an x-direction. A first elastic acoustic wave is excited in the piezoelectric film by a driving transducer and a second elastic acoustic wave generated by the Coriolis force proportional to an angular rate of the rotary motion of the angular rate sensor itself is detected by the detecting transducer. The angular rate sensor further comprises at least a first electrode disposed on the first surface of the piezoelectric film for discharging a surface charge caused due to piezoelectric effect at the lower surface of the film in which the first elastic acoustic wave is excited.

摘要翻译： 角速率传感器包括具有形成x-y平面的第一和第二表面的压电膜，并且当角速率传感器经历围绕x方向的旋转运动时，利用科里奥利力作用的扰动质量相干振动的弹性声波。 第一弹性声波通过驱动传感器在压电膜中激发，并且由与角速率传感器本身的旋转运动的角速度成比例的科里奥利力产生的第二弹性声波由检测换能器检测。 角速率传感器还包括至少第一电极，其设置在压电膜的第一表面上，用于在其中激发第一弹性声波的膜的下表面处排出由于压电效应引起的表面电荷。