公开(公告)号：US08004085B2

公开(公告)日：2011-08-23

申请号：US12593824

申请日：2008-02-13

申请人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Jun Sakai ,  Hikaru Kouta

发明人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Jun Sakai ,  Hikaru Kouta

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/10 ,  H01L29/73 ,  H01L29/74

CPC分类号： H01L23/5283 ,  H01L23/3171 ,  H01L23/5286 ,  H01L24/14 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/01047 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05099

摘要： A semiconductor device has an element interconnection 2, a top-layer element interconnection 4, a super-connect interconnection 10 and a bump 7. The element interconnection 2 is provided on a semiconductor substrate 1 through a plurality of insulating layers 50. The top-layer element interconnection 4 is formed above the element interconnection 2 by using a substantially equivalent process equipment. The super-connect interconnection 10 is provided on the top-layer element interconnection 4 through a super-connect insulating layer 9 having a thickness five or more times larger than that of the insulating layer 5, and has a thickness three or more times larger than that of each the element interconnection 2 and the top-layer element interconnection 4. The bump 7 is formed on the super-connect interconnection 10. The top-layer element interconnection 4 has a signal pad 4s, a power source pad 4v and a ground pad 4g. An area of the signal pad 4s is smaller than each area of the power source pad 4v and the ground pad 4g.

摘要翻译： 半导体器件具有元件互连2，顶层元件互连4，超连接互连10和凸块7.元件互连2通过多个绝缘层50设置在半导体衬底1上。 层元件互连4通过使用基本相同的处理设备形成在元件互连2上方。 超连接互连10通过具有比绝缘层5的厚度大五倍以上的厚度的超连接绝缘层9设置在顶层元件布线4上，并且具有比绝缘层5的厚度大三倍以上的厚度 元件互连2和顶层元件互连4中的每一个。凸块7形成在超连接互连10上。顶层元件互连4具有信号焊盘4s，电源焊盘4v和接地 垫4g。 信号焊盘4s的面积比电源焊盘4v和接地焊盘4g的面积小。

公开(公告)号：US20100117228A1

公开(公告)日：2010-05-13

申请号：US12593824

申请日：2008-02-13

申请人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Jun Sakai ,  Hikaru Kouta

发明人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Jun Sakai ,  Hikaru Kouta

IPC分类号： H01L23/52 ,  H01L23/48

CPC分类号： H01L23/5283 ,  H01L23/3171 ,  H01L23/5286 ,  H01L24/14 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/01047 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05099

摘要： A semiconductor device has an element interconnection 2, a top-layer element interconnection 4, a super-connect interconnection 10 and a bump 7. The element interconnection 2 is provided on a semiconductor substrate 1 through a plurality of insulating layers 50. The top-layer element interconnection 4 is formed above the element interconnection 2 by using a substantially equivalent process equipment. The super-connect interconnection 10 is provided on the top-layer element interconnection 4 through a super-connect insulating layer 9 having a thickness five or more times larger than that of the insulating layer 5, and has a thickness three or more times larger than that of each the element interconnection 2 and the top-layer element interconnection 4. The bump 7 is formed on the super-connect interconnection 10. The top-layer element interconnection 4 has a signal pad 4s, a power source pad 4v and a ground pad 4g. An area of the signal pad 4s is smaller than each area of the power source pad 4v and the ground pad 4g.

摘要翻译： 半导体器件具有元件互连2，顶层元件互连4，超连接互连10和凸块7.元件互连2通过多个绝缘层50设置在半导体衬底1上。 层元件互连4通过使用基本相同的处理设备形成在元件互连2上方。 超连接互连10通过具有比绝缘层5的厚度大五倍以上的厚度的超连接绝缘层9设置在顶层元件布线4上，并且具有比绝缘层5的厚度大三倍以上的厚度 元件互连2和顶层元件互连4中的每一个。凸块7形成在超连接互连10上。顶层元件互连4具有信号焊盘4s，电源焊盘4v和接地 垫4g。 信号焊盘4s的面积比电源焊盘4v和接地焊盘4g的面积小。

公开(公告)号：US20110079422A1

公开(公告)日：2011-04-07

申请号：US12994774

申请日：2008-05-26

申请人： Taras Kushita ,  Jun Sakai ,  Hikaru Kouta

发明人： Taras Kushita ,  Jun Sakai ,  Hikaru Kouta

IPC分类号： H05K1/11

CPC分类号： H05K1/0245 ,  H05K1/0251 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/09636 ,  H05K2201/09718

摘要： A multilayer substrate is provided with a conductor plane region in which a plurality of conductor planes are disposed; a clearance region disposed adjacent to the conductor plane region so that the plurality of conductor planes are excluded from the clearance region. A plurality of signal vias are disposed through the clearance region so that the plurality of signal vias are isolated from the plurality of conductor planes. A conductor post is connected to one of the plurality of conductor planes and disposed between two of the signal vias in the clearance region.

摘要翻译： 多层基板设置有布置有多个导体平面的导体平面区域; 与所述导体平面区域相邻设置的间隙区域，以使所述多个导体平面从所述间隙区域排除。 多个信号通孔设置穿过间隙区域，使得多个信号通孔与多个导体平面隔离。 导体柱连接到多个导体平面中的一个并且设置在间隙区域中的两个信号通孔之间。

公开(公告)号：US08345424B2

公开(公告)日：2013-01-01

申请号：US12865780

申请日：2009-02-16

申请人： Mikio Oda ,  Tomotaka Ishida ,  Hisaya Takahashi ,  Hideyuki Ono ,  Jun Sakai ,  Takashi Ohtsuka ,  Arihide Noda ,  Hikaru Kouta

发明人： Mikio Oda ,  Tomotaka Ishida ,  Hisaya Takahashi ,  Hideyuki Ono ,  Jun Sakai ,  Takashi Ohtsuka ,  Arihide Noda ,  Hikaru Kouta

IPC分类号： H05K7/20

CPC分类号： H01L25/167 ,  G02B6/4201 ,  G02B6/4257 ,  G02B6/4266 ,  G02B6/4274 ,  H01L2924/0002 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/00

摘要： Provided is an optical interconnection device in which a volume required for cooling is reduced. In the optical interconnection device, a plurality of optical modules (12) are arranged on a periphery of an LSI (11) electrically connected to an electric wiring board (10), and liquid cooling mechanisms (13, 14) are respectively placed on the LSI (11) and the optical modules (12). The plurality of optical modules (12) may be arranged only on a surface of the electric wiring board (10) where the LSI (11) is mounted, only on a surface opposite to the surface where the LSI (11) is mounted, or on both the same surface as and the opposite surface to the surface where the LSI (11) is mounted.

摘要翻译： 提供一种其中冷却所需的体积减小的光学互连装置。 在光互连装置中，在与电气布线板（10）电连接的LSI（11）的周围配置有多个光模块（12），液体冷却机构（13,14）分别置于 LSI（11）和光模块（12）。 多个光学模块（12）可以仅布置在安装有LSI（11）的电气布线板（10）的仅在与LSI（11）的表面相反的表面上的表面上，或者 在与安装LSI（11）的表面相同的表面上和相对的表面上。

公开(公告)号：US20090026565A1

公开(公告)日：2009-01-29

申请号：US12223541

申请日：2007-02-02

申请人： Arihide Noda ,  Mikio Oda ,  Takashi Ohtsuka ,  Hisaya Takahashi ,  Hikaru Kouta ,  Jun Sakai

发明人： Arihide Noda ,  Mikio Oda ,  Takashi Ohtsuka ,  Hisaya Takahashi ,  Hikaru Kouta ,  Jun Sakai

IPC分类号： H01L31/0232 ,  C12Q1/68 ,  G01J1/00

CPC分类号： G02B6/4214 ,  G02B6/4232 ,  G02B6/4292 ,  H01L25/167 ,  H01L31/02002 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/49109 ,  H01L2224/73253 ,  H01L2924/15192 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/184 ,  H05K3/3405 ,  H05K3/403 ,  H05K2201/10121 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/00

摘要： The present invention includes: photoelectric conversion element 103 that converts electrical signals into optical signals and optical signals into electrical signals; and optical communication LSI 102 electrically connected to photoelectric conversion element 103. Also, the present invention includes electrical wiring substrate 101 including a plurality of electrodes 201 and 202 on which photoelectric conversion element 103 and optical communication LSI 102 are mounted by flip-chip attachment and a plurality of wiring layers 101a, 101b and 101c electrically connecting respective electrodes 201 and 202, wiring layers 101a, 101b and 101c being provided at an upper surface, a lower surface and an inner portion of electrical wiring substrate 101, respectively. Also, electrodes 201 and 202 to which photoelectric conversion element 103 is bonded are provided at a side surface of electrical wiring substrate 101.

摘要翻译： 本发明包括：将电信号转换为光信号和光信号的电信号的光电转换元件103; 以及与光电转换元件103电连接的光通信LSI 102.另外，本发明包括电子布线基板101，其包括多个电极201和202，其上通过倒装芯片附接安装光电转换元件103和光通信LSI102， 电连接各个电极201和202的多个布线层101a，101b和101c，布线层101a，101b和101c分别设置在电布线基板101的上表面，下表面和内部。 而且，在电配线基板101的侧面设置与光电转换元件103接合的电极201和202。

公开(公告)号：US08536464B2

公开(公告)日：2013-09-17

申请号：US12994774

申请日：2008-05-26

申请人： Taras Kushta ,  Jun Sakai ,  Hikaru Kouta

发明人： Taras Kushta ,  Jun Sakai ,  Hikaru Kouta

IPC分类号： H05K1/11

CPC分类号： H05K1/0245 ,  H05K1/0251 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/09636 ,  H05K2201/09718

摘要： A multilayer substrate is provided with a conductor plane region in which a plurality of conductor planes are disposed; a clearance region disposed adjacent to the conductor plane region so that the plurality of conductor planes are excluded from the clearance region. A plurality of signal vias are disposed through the clearance region so that the plurality of signal vias are isolated from the plurality of conductor planes. A conductor post is connected to one of the plurality of conductor planes and disposed between two of the signal vias in the clearance region.

摘要翻译： 多层基板设置有布置有多个导体平面的导体平面区域; 与所述导体平面区域相邻设置的间隙区域，以使所述多个导体平面从所述间隙区域排除。 多个信号通孔设置穿过间隙区域，使得多个信号通孔与多个导体平面隔离。 导体柱连接到多个导体平面中的一个并且设置在间隙区域中的两个信号通孔之间。

公开(公告)号：US20100328894A1

公开(公告)日：2010-12-30

申请号：US12865780

申请日：2009-02-16

申请人： Mikio Oda ,  Tomotaka Ishida ,  Hisaya Takahashi ,  Hideyuki Ono ,  Jun Sakai ,  Takashi Ohtsuka ,  Arihide Noda ,  Hikaru Kouta

发明人： Mikio Oda ,  Tomotaka Ishida ,  Hisaya Takahashi ,  Hideyuki Ono ,  Jun Sakai ,  Takashi Ohtsuka ,  Arihide Noda ,  Hikaru Kouta

IPC分类号： H05K7/20 ,  G02B6/36

CPC分类号： H01L25/167 ,  G02B6/4201 ,  G02B6/4257 ,  G02B6/4266 ,  G02B6/4274 ,  H01L2924/0002 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/00

摘要： Provided is an optical interconnection device in which a volume required for cooling is reduced. In the optical interconnection device, a plurality of optical modules (12) are arranged on a periphery of an LSI (11) electrically connected to an electric wiring board (10), and liquid cooling mechanisms (13, 14) are respectively placed on the LSI (11) and the optical modules (12). The plurality of optical modules (12) may be arranged only on a surface of the electric wiring board (10) where the LSI (11) is mounted, only on a surface opposite to the surface where the LSI (11) is mounted, or on both the same surface as and the opposite surface to the surface where the LSI (11) is mounted.

摘要翻译： 提供一种其中冷却所需的体积减小的光学互连装置。 在光互连装置中，在与电气布线板（10）电连接的LSI（11）的周围配置多个光模块（12），液体冷却机构（13,14）分别置于 LSI（11）和光模块（12）。 多个光学模块（12）可以仅布置在安装有LSI（11）的电气布线板（10）的仅在与安装LSI（11）的表面相对的表面上，或者 在与安装LSI（11）的表面相同的表面上和相对的表面上。

公开(公告)号：US20140049343A1

公开(公告)日：2014-02-20

申请号：US14113187

申请日：2012-04-25

申请人： Jun Sakai

发明人： Jun Sakai

IPC分类号： H01P7/08

CPC分类号： H01P7/08 ,  H01P1/20345 ,  H01P7/082 ,  H05K1/0225 ,  H05K1/0243 ,  H05K1/0253 ,  H05K1/165 ,  H05K2201/09263 ,  H05K2201/09336 ,  H05K2201/09781

摘要： A circuit substrate has three wiring layers, wherein a signal line is formed in a first wiring layer; a ground plane is formed in a second wiring layer; a resonant line is formed in a third wiring layer. A circumferential slit is formed in the ground plane, wherein an island electrode separated from the ground plane is formed inside the slit. The left end of the resonant line is connected to the island electrode through an interlayer-connecting via, while the right end of the resonant line is connected to the ground plane through an interlayer-connecting via. A transmission line (or a microstrip line) is formed using the signal line and the ground plane, and therefore a complex resonator is formed to embrace the transmission line. This achieves band elimination with regard to a signal component of a resonance frequency among signals propagating through the microstrip line. Thus, it is possible to form a noise suppression structure without mounting additional parts on the circuit substrate, and therefore it is possible to effectively eliminate power distribution noise and noise propagating through the signal line with a small and simple configuration.

摘要翻译： 电路基板具有三个布线层，其中信号线形成在第一布线层中; 在第二布线层中形成接地平面; 在第三布线层中形成谐振线。 在接地平面内形成有周向狭缝，在狭缝内部形成有与接地面分离的岛状电极。 谐振线路的左端通过层间连接通孔连接到岛状电极，而谐振线路的右端通过层间连接通孔连接到接地层。 使用信号线和接地层形成传输线（或微带线），因此形成复数谐振器以包围传输线。 这实现了通过微带线传播的信号中的谐振频率的信号分量的频带消除。 因此，可以形成噪声抑制结构而不在电路基板上安装附加部件，因此可以以简单的结构有效地消除通过信号线传播的功率分配噪声和噪声。

公开(公告)号：US20130192865A1

公开(公告)日：2013-08-01

申请号：US13634782

申请日：2011-03-15

申请人： Eiji Hankui ,  Koichiro Nakase ,  Jun Sakai

发明人： Eiji Hankui ,  Koichiro Nakase ,  Jun Sakai

IPC分类号： H05K9/00

CPC分类号： H05K9/0064 ,  H04M1/19

摘要： A noise suppression structure of the present invention includes a current control unit provided on a ground layer and controlling current. The current control unit includes: a metal plane that is provided above the ground layer with an interval therebetween; and a short circuit plate that is arranged at one end portion of the metal plane, and connects the metal plane and the ground layer. A notch portion is provided in a portion of the metal plane.

摘要翻译： 本发明的噪声抑制结构包括设置在接地层上并控制电流的电流控制单元。 电流控制单元包括：金属平面，其设置在接地层上方，间隔; 以及布置在金属平面的一个端部处的短路板，并且连接金属平面和接地层。 在金属平面的一部分设有切口部分。

公开(公告)号：US20090200748A1

公开(公告)日：2009-08-13

申请号：US12425717

申请日：2009-04-17

申请人： Hiroyuki Ochiai ,  Mitsutoshi Watanabe ,  Mikiya Arai ,  Shigeru Saburi ,  Tsuyoshi Yamakawa ,  Shogo Tsugumi ,  Jun Sakai ,  Tsunao Tezuka ,  Akihiro Goto ,  Masao Akiyoshi

发明人： Hiroyuki Ochiai ,  Mitsutoshi Watanabe ,  Mikiya Arai ,  Shigeru Saburi ,  Tsuyoshi Yamakawa ,  Shogo Tsugumi ,  Jun Sakai ,  Tsunao Tezuka ,  Akihiro Goto ,  Masao Akiyoshi

IPC分类号： F16J15/447

CPC分类号： C23C26/00 ,  C23C26/02 ,  F01D5/288 ,  F01D11/122 ,  Y02T50/67 ,  Y02T50/671

摘要： A pulsed discharge is generated between tip ends of a rotating member such as a blade and a discharge electrode including a hard material such as cBN in dielectric liquid or gas by a power supply for discharge to melt the discharge electrode, and a part of the discharge electrode is attached to the tip end of the rotating member to form an abrasive coating film including the hard materials such as cBN.

摘要翻译： 在诸如叶片的旋转构件的顶端和在电介质液体中包含诸如cBN的硬质材料的放电电极或通过用于放电的电源的熔化放电电极的气体中产生脉冲放电，并且一部分放电 电极附接到旋转构件的末端，以形成包括诸如cBN的硬质材料的研磨涂层膜。