公开(公告)号：US08004085B2

公开(公告)日：2011-08-23

申请号：US12593824

申请日：2008-02-13

申请人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Jun Sakai ,  Hikaru Kouta

发明人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Jun Sakai ,  Hikaru Kouta

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/10 ,  H01L29/73 ,  H01L29/74

CPC分类号： H01L23/5283 ,  H01L23/3171 ,  H01L23/5286 ,  H01L24/14 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/01047 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05099

摘要： A semiconductor device has an element interconnection 2, a top-layer element interconnection 4, a super-connect interconnection 10 and a bump 7. The element interconnection 2 is provided on a semiconductor substrate 1 through a plurality of insulating layers 50. The top-layer element interconnection 4 is formed above the element interconnection 2 by using a substantially equivalent process equipment. The super-connect interconnection 10 is provided on the top-layer element interconnection 4 through a super-connect insulating layer 9 having a thickness five or more times larger than that of the insulating layer 5, and has a thickness three or more times larger than that of each the element interconnection 2 and the top-layer element interconnection 4. The bump 7 is formed on the super-connect interconnection 10. The top-layer element interconnection 4 has a signal pad 4s, a power source pad 4v and a ground pad 4g. An area of the signal pad 4s is smaller than each area of the power source pad 4v and the ground pad 4g.

摘要翻译： 半导体器件具有元件互连2，顶层元件互连4，超连接互连10和凸块7.元件互连2通过多个绝缘层50设置在半导体衬底1上。 层元件互连4通过使用基本相同的处理设备形成在元件互连2上方。 超连接互连10通过具有比绝缘层5的厚度大五倍以上的厚度的超连接绝缘层9设置在顶层元件布线4上，并且具有比绝缘层5的厚度大三倍以上的厚度 元件互连2和顶层元件互连4中的每一个。凸块7形成在超连接互连10上。顶层元件互连4具有信号焊盘4s，电源焊盘4v和接地 垫4g。 信号焊盘4s的面积比电源焊盘4v和接地焊盘4g的面积小。

公开(公告)号：US20100117228A1

公开(公告)日：2010-05-13

申请号：US12593824

申请日：2008-02-13

申请人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Jun Sakai ,  Hikaru Kouta

发明人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Jun Sakai ,  Hikaru Kouta

IPC分类号： H01L23/52 ,  H01L23/48

CPC分类号： H01L23/5283 ,  H01L23/3171 ,  H01L23/5286 ,  H01L24/14 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/01047 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05099

摘要： A semiconductor device has an element interconnection 2, a top-layer element interconnection 4, a super-connect interconnection 10 and a bump 7. The element interconnection 2 is provided on a semiconductor substrate 1 through a plurality of insulating layers 50. The top-layer element interconnection 4 is formed above the element interconnection 2 by using a substantially equivalent process equipment. The super-connect interconnection 10 is provided on the top-layer element interconnection 4 through a super-connect insulating layer 9 having a thickness five or more times larger than that of the insulating layer 5, and has a thickness three or more times larger than that of each the element interconnection 2 and the top-layer element interconnection 4. The bump 7 is formed on the super-connect interconnection 10. The top-layer element interconnection 4 has a signal pad 4s, a power source pad 4v and a ground pad 4g. An area of the signal pad 4s is smaller than each area of the power source pad 4v and the ground pad 4g.

摘要翻译： 半导体器件具有元件互连2，顶层元件互连4，超连接互连10和凸块7.元件互连2通过多个绝缘层50设置在半导体衬底1上。 层元件互连4通过使用基本相同的处理设备形成在元件互连2上方。 超连接互连10通过具有比绝缘层5的厚度大五倍以上的厚度的超连接绝缘层9设置在顶层元件布线4上，并且具有比绝缘层5的厚度大三倍以上的厚度 元件互连2和顶层元件互连4中的每一个。凸块7形成在超连接互连10上。顶层元件互连4具有信号焊盘4s，电源焊盘4v和接地 垫4g。 信号焊盘4s的面积比电源焊盘4v和接地焊盘4g的面积小。

公开(公告)号：US08039756B2

公开(公告)日：2011-10-18

申请号：US11542309

申请日：2006-10-04

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Yoichiro Kurita ,  Koji Soejima

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Yoichiro Kurita ,  Koji Soejima

IPC分类号： H05K1/16

CPC分类号： H01L21/6835 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K3/0023 ,  H05K3/205 ,  H05K3/4007 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2203/0733 ,  Y10T29/49128 ,  Y10T29/4913 ,  H01L2924/00012 ,  H01L2924/00

摘要： A multilayered wiring board has electrodes disposed on a first surface and a second surface, alternately layered insulation layers and wiring layers, and vias that are disposed in the insulation layer and electrically connect the wiring layers. The second electrode disposed on the second surface is embedded in the insulation layer exposed on said second surface, and the second wiring layer covered by the insulation layer exposed on said second surface does not have a layer for improving adhesion to the insulation layer.

摘要翻译： 多层布线基板具有设置在第一表面和第二表面上的电极，交替层叠的绝缘层和布线层以及布置在绝缘层中并且电连接布线层的通孔。 设置在第二表面上的第二电极嵌入在暴露在所述第二表面上的绝缘层中，并且由暴露在所述第二表面上的绝缘层覆盖的第二布线层不具有用于改善与绝缘层的粘附性的层。

公开(公告)号：US08030201B2

公开(公告)日：2011-10-04

申请号：US12635160

申请日：2009-12-10

申请人： Koji Soejima ,  Yoichiro Kurita ,  Masaya Kawano ,  Shintaro Yamamichi ,  Katsumi Kikuchi

发明人： Koji Soejima ,  Yoichiro Kurita ,  Masaya Kawano ,  Shintaro Yamamichi ,  Katsumi Kikuchi

IPC分类号： H01L21/44

CPC分类号： H01L21/563 ,  H01L21/6835 ,  H01L24/81 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1147 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A first electronic circuit component and a second electronic circuit component are electrically connected to an electro-conductive member via a first solder and a second solder, respectively. The electro-conductive member is formed in a resin film. The electro-conductive member is configured as containing a second diffusion barrier metal film. The second diffusion barrier metal film prevents diffusion of the second solder. Between the electro-conductive member and the first solder, a first diffusion barrier metal film is provided. The first diffusion barrier metal film prevents diffusion of the first solder. On the first surface of the resin film and on the electro-conductive member, an adhesive metal film is formed so as to contact with the resin film and the electro-conductive member. The adhesive metal film has stronger adhesiveness to the resin film than either of those of the first solder and the first diffusion barrier metal film.

摘要翻译： 第一电子电路部件和第二电子电路部件分别经由第一焊料和第二焊料电连接到导电部件。 导电构件形成在树脂膜中。 导电构件被构造成包含第二扩散阻挡金属膜。 第二扩散阻挡金属膜防止第二焊料的扩散。 在导电构件和第一焊料之间设置有第一扩散阻挡金属膜。 第一扩散阻挡金属膜防止第一焊料的扩散。 在树脂膜的第一表面和导电部件上形成粘接金属膜，以与树脂膜和导电部件接触。 粘合金属膜比第一焊料和第一扩散阻挡金属膜中的任一种具有比树脂膜更强的粘附性。

公开(公告)号：US07701726B2

公开(公告)日：2010-04-20

申请号：US12340267

申请日：2008-12-19

申请人： Jun Tsukano ,  Kenta Ogawa ,  Takehiko Maeda ,  Shintaro Yamamichi ,  Katsumi Kikuchi

发明人： Jun Tsukano ,  Kenta Ogawa ,  Takehiko Maeda ,  Shintaro Yamamichi ,  Katsumi Kikuchi

IPC分类号： H05K1/11 ,  H01K1/14

CPC分类号： H05K1/0271 ,  H01L21/4846 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H05K3/205 ,  H05K3/4644 ,  H05K2201/09018 ,  H05K2201/09481 ,  H05K2201/09781 ,  H01L2924/00 ,  H01L2224/0401

摘要： A wiring substrate includes a base insulating film, a first interconnection formed on a top surface side of the base insulating film, a via conductor provided in a via hole formed in the base insulating film, and a second interconnection provided on a bottom surface side of the base insulating film, the second interconnection being connected to the first interconnection via the via conductor. The wiring substrate includes divided-substrate-unit regions, in each of which the first interconnection, the via conductor, and the second interconnection are formed.

摘要翻译： 布线基板包括基底绝缘膜，形成在基底绝缘膜的上表面侧上的第一互连，设置在形成在基底绝缘膜中的通孔中的通孔导体，以及设置在基底绝缘膜的底面侧的第二互连 基底绝缘膜，第二互连件经由通孔导体连接到第一互连件。 布线基板包括分割的基板单元区域，其中形成有第一互连，通孔导体和第二互连。

公开(公告)号：US07649749B2

公开(公告)日：2010-01-19

申请号：US11822599

申请日：2007-07-09

申请人： Jun Tsukano ,  Kenta Ogawa ,  Takehiko Maeda ,  Shintaro Yamamichi ,  Katsumi Kikuchi

发明人： Jun Tsukano ,  Kenta Ogawa ,  Takehiko Maeda ,  Shintaro Yamamichi ,  Katsumi Kikuchi

IPC分类号： H05K1/11 ,  H05K1/14

CPC分类号： H05K1/0271 ,  H01L21/4846 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H05K3/205 ,  H05K3/4644 ,  H05K2201/09018 ,  H05K2201/09481 ,  H05K2201/09781 ,  H01L2924/00 ,  H01L2224/0401

摘要： A wiring substrate includes a base insulating film, a first interconnection formed on a top surface side of the base insulating film, a via conductor provided in a via formed in the base insulating film, and a second interconnection provided on a bottom surface side of the base insulating film. The second interconnection is connected to the first interconnection via the via. The wiring substrate includes divided-substrate-unit regions, in each of which the first interconnection, the via, and the second interconnection are formed. The wiring substrate includes a warpage-controlling pattern on the base insulating film, with a warped shape such that when the wiring substrate rests on a horizontal plate, at least a central part of a plane surface of the substrate contacts the horizontal plate, with both ends of the side raised.

摘要翻译： 布线基板包括基底绝缘膜，形成在基底绝缘膜的顶表面侧的第一互连，设置在形成在基底绝缘膜中的通孔中的通孔导体，以及设置在基底绝缘膜的底表面侧的第二互连 基底绝缘膜。 第二互连通过通孔连接到第一互连。 布线基板包括分开的基板单元区域，其中形成有第一互连，通孔和第二互连。 布线基板包括在基底绝缘膜上的翘曲控制图案，具有翘曲形状，使得当布线基板搁置在水平板上时，基板的平面的至少中心部分接触水平板，两者 一边抬起头。

公开(公告)号：US20090046441A1

公开(公告)日：2009-02-19

申请号：US12160132

申请日：2006-12-20

申请人： Takuo Funaya ,  Hideya Murai ,  Shintaro Yamamichi ,  Katsumi Kikuchi ,  Hirokazu Honda ,  Shinichi Miyazaki

发明人： Takuo Funaya ,  Hideya Murai ,  Shintaro Yamamichi ,  Katsumi Kikuchi ,  Hirokazu Honda ,  Shinichi Miyazaki

IPC分类号： H05K1/11 ,  H05K1/18

CPC分类号： H01L21/6835 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49866 ,  H01L24/45 ,  H01L24/48 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/19041 ,  H05K1/115 ,  H05K1/117 ,  H05K3/20 ,  H05K3/4614 ,  H05K3/4682 ,  H05K3/4694 ,  H05K2201/0272 ,  H05K2201/0352 ,  H05K2201/09845 ,  H05K2201/09972 ,  H05K2203/0425 ,  H05K2203/061 ,  H01L2924/00 ,  H01L2224/05599

摘要： A wiring board for mounting semiconductor device, includes at least a dielectric film 1; wirings formed in the dielectric film 1; a plurality of electrode pads provided at front and back surfaces of the dielectric film with their surfaces exposed and at least portions of lateral sides of them buried into the dielectric film; vias connecting the wirings and the electrode pads. At least one via connecting each other the wirings formed in the dielectric film includes second material different from first material forming the vias connecting the wirings and the electrode pads. The wiring board for mounting semiconductor device, is effective for an increase in terminals and finer pitch of terminal intervals due to an improvement in integration, performance or multi-function of semiconductor devices, can mount semiconductor devices especially on both sides of the board at a high density and high accuracy, and furthermore, is excellent in reliability as well.

摘要翻译： 一种用于安装半导体器件的布线板，至少包括电介质膜1; 电介质膜1中形成的布线; 多个电极焊盘，其设置在电介质膜的前表面和后表面，其表面暴露，并且其侧面的至少一部分埋入电介质膜中; 连接布线和电极垫的通孔。 至少一个彼此连接的通孔形成在电介质膜中的布线包括与形成连接布线和电极焊盘的通孔的第一材料不同的第二材料。 用于安装半导体器件的布线板，由于半导体器件的集成度，性能或多功能性的提高，端子间距的增加和端子间隔的更细的间距是有效的，所以可以在半导体器件的两侧特别地安装半导体器件 高密度和高精度，此外，也具有优异的可靠性。

公开(公告)号：US08710639B2

公开(公告)日：2014-04-29

申请号：US13639735

申请日：2011-02-22

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Kentaro Mori ,  Yoshiki Nakashima

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Kentaro Mori ,  Yoshiki Nakashima

IPC分类号： H01L23/02

CPC分类号： H05K1/185 ,  H01L21/6835 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L2221/68345 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/73267 ,  H01L2224/83 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/19041 ,  H05K1/0271 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2203/1469 ,  H01L2224/81 ,  H01L2924/00015 ,  H01L2224/85 ,  H01L2224/82 ,  H01L2224/45 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/48

摘要： A wiring substrate in which a semiconductor element is built includes a semiconductor element; a peripheral insulating layer covering at least an outer circumferential side surface of this semiconductor element; and an upper surface-side wiring line provided on the upper surface side of the wiring substrate. The semiconductor element includes an internal terminal electrically connected to the upper surface-side wiring line on the upper surface side of the semiconductor element. This internal terminal includes a first conductive part exposed out of an insulating surface layer of the semiconductor element; an adhesion layer on this first conductive part; and a second conductive part on this adhesion layer. The adhesion layer covers an exposed surface of the first conductive part, and is formed on a portion of the insulating surface layer around the exposed surface of the first conductive part, and the adhesion layer extends around the outer side of an outer edge of this second conductive part so as to surround the second conductive part.

摘要翻译： 构成半导体元件的布线基板包括半导体元件; 覆盖该半导体元件的至少外周侧表面的外围绝缘层; 以及设置在布线基板的上表面侧的上表面侧布线。 半导体元件包括电连接到半导体元件的上表面侧的上表面侧布线的内部端子。 该内部端子包括从半导体元件的绝缘表面层露出的第一导电部件; 在该第一导电部分上的粘附层; 和该粘合层上的第二导电部分。 粘合层覆盖第一导电部分的暴露表面，并且形成在第一导电部分的暴露表面周围的绝缘表面层的一部分上，并且粘合层围绕该第二导电部分的外边缘的外侧延伸 导电部件以包围第二导电部件。

公开(公告)号：US08692364B2

公开(公告)日：2014-04-08

申请号：US13389234

申请日：2010-08-06

申请人： Katsumi Kikuchi ,  Yoshiki Nakashima ,  Kentaro Mori ,  Shintaro Yamamichi

发明人： Katsumi Kikuchi ,  Yoshiki Nakashima ,  Kentaro Mori ,  Shintaro Yamamichi

IPC分类号： H01L23/06 ,  H01L23/48 ,  H01L23/02 ,  H01L23/522 ,  H01L21/4763 ,  H01L21/48

CPC分类号： H05K1/185 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24226 ,  H01L2224/73267 ,  H01L2224/92 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/3511 ,  H05K1/0366 ,  H05K3/4682 ,  H05K2201/029 ,  H05K2201/10674 ,  H05K2203/063 ,  H05K2203/1469 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： A semiconductor device includes an embedding layer in which one or more semiconductor element(s) is embedded and one or more interconnect layers as well as one or more insulation layers on one or both sides of the embedding layer. The embedding layer includes a woven cloth formed by reinforcement fibers. The woven cloth has an opening on its site embedding the semiconductor element. The opening is arranged so that direction of the reinforcement fibers will have a preset angle with respect to a direction of a side of or a tangent to at least a portion of the opening, the preset angle being other than a square angle or a zero angle (parallelism).

摘要翻译： 一种半导体器件包括其中嵌入一个或多个半导体元件的嵌入层和一个或多个互连层以及在嵌入层的一侧或两侧上的一个或多个绝缘层。 嵌入层包括由增强纤维形成的织布。 编织布在其内部具有嵌入半导体元件的开口。 开口被布置成使得加强纤维的方向相对于开口的至少一部分的一侧的方向或切线的方向具有预设角度，预设角度不同于方角或零角度 （并行）。

公开(公告)号：US08569892B2

公开(公告)日：2013-10-29

申请号：US13062262

申请日：2009-10-05

申请人： Kentaro Mori ,  Daisuke Ohshima ,  Shintaro Yamamichi ,  Hideya Murai ,  Katsumi Maeda ,  Katsumi Kikuchi ,  Yoshiki Nakashima

发明人： Kentaro Mori ,  Daisuke Ohshima ,  Shintaro Yamamichi ,  Hideya Murai ,  Katsumi Maeda ,  Katsumi Kikuchi ,  Yoshiki Nakashima

IPC分类号： H01L23/48 ,  H01L23/10

CPC分类号： H01L24/85 ,  H01L23/13 ,  H01L23/142 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/24 ,  H01L24/28 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/91 ,  H01L24/92 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/2402 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/85 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A semiconductor device includes: at least one semiconductor element having electrode terminals; a metal plate supporting the semiconductor element; and a wiring board covering the semiconductor element and including a plurality of insulating layers and wiring layers alternately stacked and external connection terminals on a surface, the wiring layers being electrically connected to each other by vias. The electrode terminals and the external connection terminals are electrically connected via at least one of the wiring layers and the vias. At least one of the electrode terminals, the is wiring layers, and the vias is electrically connected to the metal plate.

摘要翻译： 半导体器件包括：至少一个具有电极端子的半导体元件; 支撑半导体元件的金属板; 以及覆盖半导体元件并且在表面上交替堆叠的多个绝缘层和布线层以及外部连接端子的布线板，布线层通过通孔彼此电连接。 电极端子和外部连接端子经由布线层和通孔中的至少一个电连接。 至少一个电极端子，即布线层和通孔，电连接到金属板。