公开(公告)号：US08710639B2

公开(公告)日：2014-04-29

申请号：US13639735

申请日：2011-02-22

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Kentaro Mori ,  Yoshiki Nakashima

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Kentaro Mori ,  Yoshiki Nakashima

IPC分类号： H01L23/02

CPC分类号： H05K1/185 ,  H01L21/6835 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L2221/68345 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/73267 ,  H01L2224/83 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/19041 ,  H05K1/0271 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2203/1469 ,  H01L2224/81 ,  H01L2924/00015 ,  H01L2224/85 ,  H01L2224/82 ,  H01L2224/45 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/48

摘要： A wiring substrate in which a semiconductor element is built includes a semiconductor element; a peripheral insulating layer covering at least an outer circumferential side surface of this semiconductor element; and an upper surface-side wiring line provided on the upper surface side of the wiring substrate. The semiconductor element includes an internal terminal electrically connected to the upper surface-side wiring line on the upper surface side of the semiconductor element. This internal terminal includes a first conductive part exposed out of an insulating surface layer of the semiconductor element; an adhesion layer on this first conductive part; and a second conductive part on this adhesion layer. The adhesion layer covers an exposed surface of the first conductive part, and is formed on a portion of the insulating surface layer around the exposed surface of the first conductive part, and the adhesion layer extends around the outer side of an outer edge of this second conductive part so as to surround the second conductive part.

摘要翻译： 构成半导体元件的布线基板包括半导体元件; 覆盖该半导体元件的至少外周侧表面的外围绝缘层; 以及设置在布线基板的上表面侧的上表面侧布线。 半导体元件包括电连接到半导体元件的上表面侧的上表面侧布线的内部端子。 该内部端子包括从半导体元件的绝缘表面层露出的第一导电部件; 在该第一导电部分上的粘附层; 和该粘合层上的第二导电部分。 粘合层覆盖第一导电部分的暴露表面，并且形成在第一导电部分的暴露表面周围的绝缘表面层的一部分上，并且粘合层围绕该第二导电部分的外边缘的外侧延伸 导电部件以包围第二导电部件。

公开(公告)号：US08692364B2

公开(公告)日：2014-04-08

申请号：US13389234

申请日：2010-08-06

申请人： Katsumi Kikuchi ,  Yoshiki Nakashima ,  Kentaro Mori ,  Shintaro Yamamichi

发明人： Katsumi Kikuchi ,  Yoshiki Nakashima ,  Kentaro Mori ,  Shintaro Yamamichi

IPC分类号： H01L23/06 ,  H01L23/48 ,  H01L23/02 ,  H01L23/522 ,  H01L21/4763 ,  H01L21/48

CPC分类号： H05K1/185 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24226 ,  H01L2224/73267 ,  H01L2224/92 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/3511 ,  H05K1/0366 ,  H05K3/4682 ,  H05K2201/029 ,  H05K2201/10674 ,  H05K2203/063 ,  H05K2203/1469 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： A semiconductor device includes an embedding layer in which one or more semiconductor element(s) is embedded and one or more interconnect layers as well as one or more insulation layers on one or both sides of the embedding layer. The embedding layer includes a woven cloth formed by reinforcement fibers. The woven cloth has an opening on its site embedding the semiconductor element. The opening is arranged so that direction of the reinforcement fibers will have a preset angle with respect to a direction of a side of or a tangent to at least a portion of the opening, the preset angle being other than a square angle or a zero angle (parallelism).

摘要翻译： 一种半导体器件包括其中嵌入一个或多个半导体元件的嵌入层和一个或多个互连层以及在嵌入层的一侧或两侧上的一个或多个绝缘层。 嵌入层包括由增强纤维形成的织布。 编织布在其内部具有嵌入半导体元件的开口。 开口被布置成使得加强纤维的方向相对于开口的至少一部分的一侧的方向或切线的方向具有预设角度，预设角度不同于方角或零角度 （并行）。

公开(公告)号：US08569892B2

公开(公告)日：2013-10-29

申请号：US13062262

申请日：2009-10-05

申请人： Kentaro Mori ,  Daisuke Ohshima ,  Shintaro Yamamichi ,  Hideya Murai ,  Katsumi Maeda ,  Katsumi Kikuchi ,  Yoshiki Nakashima

发明人： Kentaro Mori ,  Daisuke Ohshima ,  Shintaro Yamamichi ,  Hideya Murai ,  Katsumi Maeda ,  Katsumi Kikuchi ,  Yoshiki Nakashima

IPC分类号： H01L23/48 ,  H01L23/10

CPC分类号： H01L24/85 ,  H01L23/13 ,  H01L23/142 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/24 ,  H01L24/28 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/91 ,  H01L24/92 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/2402 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/85 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A semiconductor device includes: at least one semiconductor element having electrode terminals; a metal plate supporting the semiconductor element; and a wiring board covering the semiconductor element and including a plurality of insulating layers and wiring layers alternately stacked and external connection terminals on a surface, the wiring layers being electrically connected to each other by vias. The electrode terminals and the external connection terminals are electrically connected via at least one of the wiring layers and the vias. At least one of the electrode terminals, the is wiring layers, and the vias is electrically connected to the metal plate.

摘要翻译： 半导体器件包括：至少一个具有电极端子的半导体元件; 支撑半导体元件的金属板; 以及覆盖半导体元件并且在表面上交替堆叠的多个绝缘层和布线层以及外部连接端子的布线板，布线层通过通孔彼此电连接。 电极端子和外部连接端子经由布线层和通孔中的至少一个电连接。 至少一个电极端子，即布线层和通孔，电连接到金属板。

公开(公告)号：US20120300425A1

公开(公告)日：2012-11-29

申请号：US13574455

申请日：2011-01-07

申请人： Yoshiki Nakashima ,  Shintaro Yamamichi ,  Katsumi Kikuchi ,  Kentaro Mori ,  Hideya Murai

发明人： Yoshiki Nakashima ,  Shintaro Yamamichi ,  Katsumi Kikuchi ,  Kentaro Mori ,  Hideya Murai

IPC分类号： H05K1/18 ,  H05K1/11

CPC分类号： H05K1/182 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/18162 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/185 ,  Y10T29/49126 ,  Y10T29/49165 ,  Y10T428/24322 ,  H01L2924/00

摘要： An object of the present invention is to propose a functional element built-in substrate which enables an electrode terminal of a functional element to be well connected to the back surface on the side opposite to the electrode terminal of the functional element, and which can be miniaturized. According to the present invention, there is provided a functional element built-in substrate including a functional element provided with an electrode terminal on one surface side of the functional element, and a wiring substrate including a laminated structure in which the functional element is embedded so that the electrode terminal of the functional element faces the front surface side of the structure, and which is formed at least in a side surface region of the functional element by laminating a plurality of wiring insulating layers each including a wiring, the functional element built-in substrate being featured in that the electrode terminal and the back surface side of the wiring substrate are electrically connected to each other through the wiring of the laminated structure, and in that, in a pair of the wiring insulating layers included in the laminated structure and that are in contact with each other, the cross-sectional shape of the wiring in each of the wiring insulating layers, which cross-sectional shape is taken along the plane perpendicular to the extension direction of the wiring in the wiring insulating layer, has a relationship that the cross-sectional area of the wiring in the back surface side wiring insulating layer is larger than the cross-sectional area of the wiring in the front surface side wiring insulating layer.

摘要翻译： 本发明的目的是提出一种功能元件内置基板，其使功能元件的电极端子能够良好地连接到与功能元件的电极端子相反的一侧的背面，并且其可以是 小型化。 根据本发明，提供了一种功能元件内置基板，其包括在功能元件的一个表面侧上设置有电极端子的功能元件，以及包括功能元件嵌入其中的层叠结构的布线基板 所述功能元件的电极端子面向所述结构的前表面侧，并且通过层叠多个布线绝缘层而形成在所述功能元件的至少侧面区域中，所述多个布线绝缘层包括布线， 其特征在于，布线基板的电极端子和背面侧通过层叠结构的布线电连接，并且其中，在层叠结构中包括的一对布线绝缘层和 彼此接触，每个布线绝缘中的布线的横截面形状 与布线绝缘层中的配线的延伸方向垂直的平面截取的截面形状的层具有这样的关系：背面侧配线绝缘层中的布线的截面积大于 表面侧配线绝缘层中的配线的截面积。

公开(公告)号：US20120133052A1

公开(公告)日：2012-05-31

申请号：US13389234

申请日：2010-08-06

申请人： Katsumi Kikuchi ,  Yoshiki Nakashima ,  Kentaro Mori ,  Shintaro Yamamichi

发明人： Katsumi Kikuchi ,  Yoshiki Nakashima ,  Kentaro Mori ,  Shintaro Yamamichi

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H05K1/185 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24226 ,  H01L2224/73267 ,  H01L2224/92 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/3511 ,  H05K1/0366 ,  H05K3/4682 ,  H05K2201/029 ,  H05K2201/10674 ,  H05K2203/063 ,  H05K2203/1469 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： A semiconductor device includes an embedding layer in which one or more semiconductor element(s) is embedded and one or more interconnect layers as well as one or more insulation layers on one or both sides of the embedding layer. The embedding layer includes a woven cloth formed by reinforcement fibers. The woven cloth has an opening on its site embedding the semiconductor element. The opening is arranged so that direction of the reinforcement fibers will have a preset angle with respect to a direction of a side of or a tangent to at least a portion of the opening, the preset angle being other than a square angle or a zero angle (parallelism).

摘要翻译： 一种半导体器件包括其中嵌入一个或多个半导体元件的嵌入层和一个或多个互连层以及在嵌入层的一侧或两侧上的一个或多个绝缘层。 嵌入层包括由增强纤维形成的织布。 编织布在其内部具有嵌入半导体元件的开口。 开口被布置成使得加强纤维的方向相对于开口的至少一部分的一侧的方向或切线的方向具有预设角度，预设角度不同于方角或零角度 （并行）。

公开(公告)号：US08050050B2

公开(公告)日：2011-11-01

申请号：US12960148

申请日：2010-12-03

申请人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Yoichiro Kurita ,  Koji Soejima

发明人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Yoichiro Kurita ,  Koji Soejima

IPC分类号： H05K1/11

CPC分类号： H01L23/49816 ,  H01L21/6835 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor device comprising a flat wiring board, a first LSI disposed on one surface of the wiring board, a sealing resin for covering the one surface and a side face of the first semiconductor element, and a second LSI disposed on another surface of the wiring board. The wiring board has conductive wiring as a wiring layer, an insulation resin as a support layer for the wiring layer, and a conductive through-hole that passes through the wiring layer and the support layer. Connection points between lands disposed in positions in which the external peripheral edges of the semiconductor elements transverse the interior of the lands as viewed vertically from above, which lands are selected from land portions on which the external connection terminals are formed, and the wiring board formed in the same plane as the lands, are unevenly distributed toward one side of the wiring board. Connections for very small wiring are thereby made possible, and a plurality of semiconductor elements can be very densely connected.

公开(公告)号：US08004085B2

公开(公告)日：2011-08-23

申请号：US12593824

申请日：2008-02-13

申请人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Jun Sakai ,  Hikaru Kouta

发明人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Jun Sakai ,  Hikaru Kouta

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/10 ,  H01L29/73 ,  H01L29/74

CPC分类号： H01L23/5283 ,  H01L23/3171 ,  H01L23/5286 ,  H01L24/14 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/01047 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05099

摘要： A semiconductor device has an element interconnection 2, a top-layer element interconnection 4, a super-connect interconnection 10 and a bump 7. The element interconnection 2 is provided on a semiconductor substrate 1 through a plurality of insulating layers 50. The top-layer element interconnection 4 is formed above the element interconnection 2 by using a substantially equivalent process equipment. The super-connect interconnection 10 is provided on the top-layer element interconnection 4 through a super-connect insulating layer 9 having a thickness five or more times larger than that of the insulating layer 5, and has a thickness three or more times larger than that of each the element interconnection 2 and the top-layer element interconnection 4. The bump 7 is formed on the super-connect interconnection 10. The top-layer element interconnection 4 has a signal pad 4s, a power source pad 4v and a ground pad 4g. An area of the signal pad 4s is smaller than each area of the power source pad 4v and the ground pad 4g.

摘要翻译： 半导体器件具有元件互连2，顶层元件互连4，超连接互连10和凸块7.元件互连2通过多个绝缘层50设置在半导体衬底1上。 层元件互连4通过使用基本相同的处理设备形成在元件互连2上方。 超连接互连10通过具有比绝缘层5的厚度大五倍以上的厚度的超连接绝缘层9设置在顶层元件布线4上，并且具有比绝缘层5的厚度大三倍以上的厚度 元件互连2和顶层元件互连4中的每一个。凸块7形成在超连接互连10上。顶层元件互连4具有信号焊盘4s，电源焊盘4v和接地 垫4g。 信号焊盘4s的面积比电源焊盘4v和接地焊盘4g的面积小。

公开(公告)号：US07816782B2

公开(公告)日：2010-10-19

申请号：US11174526

申请日：2005-07-06

申请人： Hideya Murai ,  Tadanori Shimoto ,  Takuo Funaya ,  Katsumi Kikuchi ,  Shintaro Yamamichi ,  Kazuhiro Baba ,  Hirokazu Honda ,  Keiichiro Kata ,  Kouji Matsui ,  Shinichi Miyazaki

发明人： Hideya Murai ,  Tadanori Shimoto ,  Takuo Funaya ,  Katsumi Kikuchi ,  Shintaro Yamamichi ,  Kazuhiro Baba ,  Hirokazu Honda ,  Keiichiro Kata ,  Kouji Matsui ,  Shinichi Miyazaki

IPC分类号： H01L23/14 ,  H01L23/12

CPC分类号： H01L21/4857 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/181 ,  H05K3/007 ,  H05K3/205 ,  H05K3/28 ,  H05K3/4614 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2203/0152 ,  H05K2203/061 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the rear surface of the insulation film, and at least a part of the side surface of the electrode pads is buried in the insulation film. The insulation film is formed by forming electrode pads on the respective two metallic plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad, and adhering the insulation layers to each other for integration, and thereafter, removing the metallic plates.

摘要翻译： 用于安装半导体的布线基板设置有绝缘膜，形成在绝缘膜中的布线以及通过通孔电连接到导线的多个电极垫。 电极焊盘被设置为使其表面暴露于绝缘膜的前表面和后表面，并且电极焊盘的侧表面的至少一部分被埋在绝缘膜中。 绝缘膜通过在相应的两个金属板上形成电极焊盘而形成，然后在相应的金属板上层叠绝缘层和电线以覆盖电极焊盘，并将绝缘层彼此粘合在一起，然后除去 金属板。

公开(公告)号：US07784653B2

公开(公告)日：2010-08-31

申请号：US11199131

申请日：2005-08-09

申请人： Katsumi Kikuchi

发明人： Katsumi Kikuchi

IPC分类号： B65D5/72 ,  B65D83/00 ,  B65D35/38 ,  B43K5/18 ,  B43K7/04 ,  B43K5/00 ,  B43K5/16 ,  B67D3/00

CPC分类号： B05C17/00503 ,  B05C5/02 ,  H01L21/67126

摘要： By means of a fluid material discharge device of simple construction, a technique for fluid material discharge is provided which has few or no inadequate discharge, high productivity, and which enables easy modification and adjustment of the amount of fluid material discharge. The fluid material discharge device comprises a nozzle for discharge of fluid material and a filament-shape member inserted into the nozzle for use. The filament-shape member has a tip portion AA, which is exposed outside of the nozzle when no pressure is exerted on the tip of the filament-shape member, a portion BB which can be inserted into the nozzle, and a portion CC, on the side of the filament-shape member opposite the tip portion AA, and being bent from the portion BB. The spring structure of the filament-shape member is utilized to discharge fluid material.

摘要翻译： 通过简单结构的流体物料排出装置，提供了一种液体材料排出技术，其排放量很少或排放不足，生产率高，能够容易地改变和调节流体材料的排出量。 流体材料排出装置包括用于排出流体材料的喷嘴和插入喷嘴中的丝状构件用于使用。 长丝状构件具有尖端部AA，当没有压力施加在丝状构件的顶端上时，暴露在喷嘴外部，可以插入到喷嘴中的部分BB和部分CC 长丝状部件的与末端部分AA相对的一侧，并从部分BB弯曲。 丝状构件的弹簧结构用于排出流体材料。

公开(公告)号：US20100117228A1

公开(公告)日：2010-05-13

申请号：US12593824

申请日：2008-02-13

申请人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Jun Sakai ,  Hikaru Kouta

发明人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Jun Sakai ,  Hikaru Kouta

IPC分类号： H01L23/52 ,  H01L23/48

CPC分类号： H01L23/5283 ,  H01L23/3171 ,  H01L23/5286 ,  H01L24/14 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/01047 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05099

摘要： A semiconductor device has an element interconnection 2, a top-layer element interconnection 4, a super-connect interconnection 10 and a bump 7. The element interconnection 2 is provided on a semiconductor substrate 1 through a plurality of insulating layers 50. The top-layer element interconnection 4 is formed above the element interconnection 2 by using a substantially equivalent process equipment. The super-connect interconnection 10 is provided on the top-layer element interconnection 4 through a super-connect insulating layer 9 having a thickness five or more times larger than that of the insulating layer 5, and has a thickness three or more times larger than that of each the element interconnection 2 and the top-layer element interconnection 4. The bump 7 is formed on the super-connect interconnection 10. The top-layer element interconnection 4 has a signal pad 4s, a power source pad 4v and a ground pad 4g. An area of the signal pad 4s is smaller than each area of the power source pad 4v and the ground pad 4g.

摘要翻译： 半导体器件具有元件互连2，顶层元件互连4，超连接互连10和凸块7.元件互连2通过多个绝缘层50设置在半导体衬底1上。 层元件互连4通过使用基本相同的处理设备形成在元件互连2上方。 超连接互连10通过具有比绝缘层5的厚度大五倍以上的厚度的超连接绝缘层9设置在顶层元件布线4上，并且具有比绝缘层5的厚度大三倍以上的厚度 元件互连2和顶层元件互连4中的每一个。凸块7形成在超连接互连10上。顶层元件互连4具有信号焊盘4s，电源焊盘4v和接地 垫4g。 信号焊盘4s的面积比电源焊盘4v和接地焊盘4g的面积小。