公开(公告)号：US09230826B2

公开(公告)日：2016-01-05

申请号：US13213130

申请日：2011-08-19

申请人： Shinya Sasagawa ,  Hiroshi Fujiki ,  Shinobu Furukawa ,  Hidekazu Miyairi

发明人： Shinya Sasagawa ,  Hiroshi Fujiki ,  Shinobu Furukawa ,  Hidekazu Miyairi

IPC分类号： H01L21/20 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L21/32137 ,  H01L29/6675 ,  H01L29/66765 ,  H01L29/78663 ,  H01L29/78669 ,  H01L29/78672 ,  H01L29/78678 ,  H01L29/78687

摘要： A method for etching is provided in which the etching selectivity of an amorphous semiconductor film to a crystalline semiconductor film is high. Part of a stacked semiconductor film in which an amorphous semiconductor film is provided on a crystalline semiconductor film is etched using a mixed gas of a Br-based gas, a F-based gas, and an oxygen gas, so that part of the crystalline semiconductor film provided in the stacked semiconductor film is exposed. Reduction in the film thickness of the exposed portion can be suppressed by performing the etching in such a manner. Moreover, when etching for forming a back channel portion of a thin film transistor is performed with the method for etching, favorable electric characteristics of the thin film transistor can be obtained. An insulating layer is preferably provided over the thin film transistor.

摘要翻译： 提供了一种用于蚀刻的方法，其中非晶半导体膜对结晶半导体膜的蚀刻选择性高。 使用Br基气体，F系气体和氧气的混合气体蚀刻在结晶半导体膜上设置非晶半导体膜的层叠半导体膜的一部分，使部分结晶半导体 提供在堆叠的半导体膜中的膜被暴露。 可以通过以这种方式进行蚀刻来抑制曝光部分的膜厚度的降低。 此外，当利用蚀刻方法进行用于形成薄膜晶体管的背沟道部分的蚀刻时，可以获得薄膜晶体管的良好的电特性。 绝缘层优选设置在薄膜晶体管的上方。

公开(公告)号：US20090061573A1

公开(公告)日：2009-03-05

申请号：US12230048

申请日：2008-08-22

申请人： Hidekazu Miyairi ,  Shinya Sasagawa ,  Akihiro Ishizuka

发明人： Hidekazu Miyairi ,  Shinya Sasagawa ,  Akihiro Ishizuka

IPC分类号： H01L21/336

CPC分类号： H01L29/6675 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78696 ,  H01L33/0058 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a method for manufacturing a highly reliable semiconductor device with a small amount of leakage current. In a method for manufacturing a thin film transistor, etching is conducted using a resist mask to form a back channel portion in the thin film transistor, the resist mask is removed, a part of the back channel is etched to remove etching residue and the like left over the back channel portion, whereby leakage current caused by the residue and the like can be reduced. The etching step of the back channel portion can be conducted by dry etching using non-bias.

摘要翻译： 本发明提供了一种制造具有少量漏电流的高可靠性半导体器件的方法。 在制造薄膜晶体管的方法中，使用抗蚀剂掩模进行蚀刻以在薄膜晶体管中形成背沟道部分，去除抗蚀剂掩模，蚀刻一部分后沟道以除去蚀刻残留物等 留在后通道部分，由此可以减少由残渣等引起的泄漏电流。 背沟道部分的蚀刻步骤可以通过使用非偏压的干蚀刻来进行。

公开(公告)号：US08349671B2

公开(公告)日：2013-01-08

申请号：US12230048

申请日：2008-08-22

申请人： Hidekazu Miyairi ,  Shinya Sasagawa ,  Akihiro Ishizuka

发明人： Hidekazu Miyairi ,  Shinya Sasagawa ,  Akihiro Ishizuka

IPC分类号： H01L21/336

CPC分类号： H01L29/6675 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78696 ,  H01L33/0058 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a method for manufacturing a highly reliable semiconductor device with a small amount of leakage current. In a method for manufacturing a thin film transistor, etching is conducted using a resist mask to form a back channel portion in the thin film transistor, the resist mask is removed, a part of the back channel is etched to remove etching residue and the like left over the back channel portion, whereby leakage current caused by the residue and the like can be reduced. The etching step of the back channel portion can be conducted by dry etching using non-bias.

公开(公告)号：US08829522B2

公开(公告)日：2014-09-09

申请号：US12972994

申请日：2010-12-20

申请人： Hidekazu Miyairi ,  Shinya Sasagawa ,  Motomu Kurata

发明人： Hidekazu Miyairi ,  Shinya Sasagawa ,  Motomu Kurata

IPC分类号： H01L29/786

CPC分类号： H01L29/78678 ,  H01L29/66765 ,  H01L29/78618 ,  H01L29/78648

摘要： A thin film transistor having favorable electric characteristics with high productively is provided. The thin film transistor includes a gate insulating layer covering a gate electrode, a semiconductor layer in contact with the gate insulating layer, an impurity semiconductor layer which is in contact with part of the semiconductor layer and functions as a source region and a drain region, and a wiring in contact with the impurity semiconductor layer. The semiconductor layer includes a microcrystalline semiconductor region having a concave-convex shape, which is formed on the gate insulating layer side, and an amorphous semiconductor region in contact with the microcrystalline semiconductor region. A barrier region is provided between the semiconductor layer and the wiring.

摘要翻译： 提供了具有良好的电特性的高效生产的薄膜晶体管。 薄膜晶体管包括覆盖栅极的栅极绝缘层，与栅极绝缘层接触的半导体层，与半导体层的一部分接触并用作源极区域和漏极区域的杂质半导体层， 以及与杂质半导体层接触的布线。 半导体层包括形成在栅绝缘层侧的具有凹凸形状的微晶半导体区域和与微晶半导体区域接触的非晶半导体区域。 在半导体层和布线之间设置有阻挡区域。

公开(公告)号：US09454048B2

公开(公告)日：2016-09-27

申请号：US13416077

申请日：2012-03-09

申请人： Hidekazu Miyairi ,  Tetsuji Ishitani ,  Daisuke Kubota ,  Shinya Sasagawa

发明人： Hidekazu Miyairi ,  Tetsuji Ishitani ,  Daisuke Kubota ,  Shinya Sasagawa

IPC分类号： G02F1/1343 ,  C09K19/02 ,  G02F1/1362

CPC分类号： G02F1/134363 ,  C09K19/0275 ,  G02F1/1362

摘要： A horizontal electric field mode liquid crystal display device having a novel electrode structure, and a manufacturing method thereof are provided. The liquid crystal display device includes a first substrate having an insulating surface; a first conductive film and a second conductive film over the insulating surface; a first insulating film over the first conductive film; a second insulating film over the second conductive film; a second substrate facing the first substrate; and a liquid crystal layer positioned between the first substrate and the second substrate. Part of the first conductive film exists also on a side portion of the first insulating film, and part of the second conductive film exists also on a side portion of the second insulating film. The liquid crystal layer includes liquid crystal exhibiting a blue phase.

摘要翻译： 提供具有新型电极结构的水平电场模式液晶显示装置及其制造方法。 液晶显示装置包括具有绝缘面的第一基板; 绝缘表面上的第一导电膜和第二导电膜; 第一导电膜上的第一绝缘膜; 在第二导电膜上的第二绝缘膜; 面对所述第一基板的第二基板; 以及位于第一基板和第二基板之间的液晶层。 第一导电膜的一部分也存在于第一绝缘膜的侧部，第二导电膜的一部分也存在于第二绝缘膜的侧部。 液晶层包括呈蓝色相的液晶。

公开(公告)号：US08546810B2

公开(公告)日：2013-10-01

申请号：US12788343

申请日：2010-05-27

申请人： Hidekazu Miyairi ,  Yasuhiro Jinbo ,  Hiromichi Godo ,  Takafumi Mizoguchi ,  Shinobu Furukawa

发明人： Hidekazu Miyairi ,  Yasuhiro Jinbo ,  Hiromichi Godo ,  Takafumi Mizoguchi ,  Shinobu Furukawa

IPC分类号： H01L27/14 ,  H01L29/04 ,  H01L29/15 ,  H01L31/036

CPC分类号： H01L29/78621 ,  H01L29/04 ,  H01L29/66765

摘要： A thin film transistor in which an effect of photo current is small and an On/Off ratio is high is provided. In a bottom-gate bottom-contact (coplanar) thin film transistor, a channel formation region overlaps with a gate electrode, a first impurity semiconductor layer is provided between the channel formation region and a second impurity semiconductor layer which is in contact with a wiring layer. A semiconductor layer which serves as the channel formation region and the first impurity semiconductor layer preferably overlap with each other in a region where they overlap with the gate electrode. The first impurity semiconductor layer and the second impurity semiconductor layer preferably overlap with each other in a region where they do not overlap with the gate electrode.

摘要翻译： 提供其中光电流的作用小且开/关比高的薄膜晶体管。 在底栅底接触（共面）薄膜晶体管中，沟道形成区域与栅电极重叠，在沟道形成区域和与布线接触的第二杂质半导体层之间设置第一杂质半导体层 层。 用作沟道形成区域和第一杂质半导体层的半导体层优选在与栅电极重叠的区域中彼此重叠。 第一杂质半导体层和第二杂质半导体层优选在不与栅电极重叠的区域中彼此重叠。

公开(公告)号：US09496406B2

公开(公告)日：2016-11-15

申请号：US13547377

申请日：2012-07-12

申请人： Shunpei Yamazaki ,  Hidekazu Miyairi ,  Akiharu Miyanaga ,  Kengo Akimoto ,  Kojiro Shiraishi

发明人： Shunpei Yamazaki ,  Hidekazu Miyairi ,  Akiharu Miyanaga ,  Kengo Akimoto ,  Kojiro Shiraishi

IPC分类号： H01L29/786 ,  H01L27/12

CPC分类号： H01L29/78618 ,  G02F1/133345 ,  G02F1/133528 ,  G02F1/134336 ,  G02F1/13439 ,  G02F1/136286 ,  G02F1/1368 ,  G02F1/167 ,  G02F2201/123 ,  G09G3/3674 ,  G09G2310/0286 ,  H01L27/1225 ,  H01L27/3262 ,  H01L29/247 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

摘要： An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.

摘要翻译： 一个实施例是包括反向交错（底栅结构）薄膜晶体管，其中使用含有In，Ga和Zn的氧化物半导体膜作为半导体层，并且缓冲层设置在半导体层与源极和漏极之间 电极层。 有意地在源极和漏极电极层与半导体层之间提供具有比半导体层高的载流子浓度的缓冲层，从而形成欧姆接触。

公开(公告)号：US09401396B2

公开(公告)日：2016-07-26

申请号：US13433563

申请日：2012-03-29

申请人： Kanta Abe ,  Hidekazu Miyairi ,  Tetsuhiro Tanaka ,  Takashi Ienaga ,  Yoshitaka Yamamoto

发明人： Kanta Abe ,  Hidekazu Miyairi ,  Tetsuhiro Tanaka ,  Takashi Ienaga ,  Yoshitaka Yamamoto

IPC分类号： H01L21/20 ,  H01L21/36 ,  H01L29/04 ,  H01L29/66 ,  H01L21/28 ,  H01L29/786

CPC分类号： H01L29/04 ,  H01L21/28008 ,  H01L29/66765 ,  H01L29/786 ,  H01L29/78648 ,  H01L29/78678 ,  H01L29/78696

摘要： Provided is a method for manufacturing a semiconductor device, in which a degradation of characteristics of a thin film transistor can be suppressed by performing plasma oxidation treatment on a gate insulating film containing nitrogen. An embodiment of the present invention is a method for manufacturing a semiconductor device comprising a thin film transistor including a gate electrode, a gate insulating film containing nitrogen, and a channel region in microcrystalline semiconductor films. The method includes the steps of performing plasma treatment on the gate insulating film in an oxidizing gas atmosphere containing hydrogen and an oxidizing gas containing an oxygen atom, and forming the microcrystalline semiconductor film over the gate insulating film. Formula (1), a/b≧2, and Formula (2), b>0, are satisfied, where the amount of hydrogen and the amount of the oxidizing gas in the oxidizing gas atmosphere are a and b, respectively.

摘要翻译： 提供一种半导体器件的制造方法，其中通过对含有氮的栅极绝缘膜进行等离子体氧化处理可以抑制薄膜晶体管的特性的劣化。 本发明的一个实施例是一种半导体器件的制造方法，该半导体器件包括薄膜晶体管，该薄膜晶体管包括栅电极，含氮的栅绝缘膜和微晶半导体膜中的沟道区。 该方法包括以下步骤：在包含氢的氧化气体气氛和含有氧原子的氧化气体的栅极绝缘膜上进行等离子体处理，并在栅极绝缘膜上形成微晶半导体膜。 满足式（1），a /b≥2和式（2），b> 0，其中，氢和氧化气体气氛中的氧化气体量分别为a和b。

公开(公告)号：US09176353B2

公开(公告)日：2015-11-03

申请号：US12213728

申请日：2008-06-24

申请人： Shunpei Yamazaki ,  Yukie Suzuki ,  Hideaki Kuwabara ,  Hajime Kimura ,  Hidekazu Miyairi ,  Yoshiyuki Kurokawa ,  Satoshi Kobayashi

发明人： Shunpei Yamazaki ,  Yukie Suzuki ,  Hideaki Kuwabara ,  Hajime Kimura ,  Hidekazu Miyairi ,  Yoshiyuki Kurokawa ,  Satoshi Kobayashi

IPC分类号： G02F1/136 ,  G02F1/1368 ,  H01L21/67

CPC分类号： G02F1/1368 ,  G02F1/133345 ,  H01L21/67207 ,  H01L29/41733 ,  H01L29/66765 ,  H01L29/78678 ,  H01L29/78696

摘要： An object is to propose a method of manufacturing, with high mass productivity, liquid crystal display devices having thin film transistors with highly reliable electric characteristics. In a liquid crystal display device having an inverted staggered thin film transistor, the inverted staggered thin film transistor is formed as follows: a gate insulating film is formed over a gate electrode; a microcrystalline semiconductor film which functions as a channel formation region is formed over the gate insulating film; a buffer layer is formed over the microcrystalline semiconductor film; a pair of source and drain regions are formed over the buffer layer; and a pair of source and drain electrodes are formed in contact with the source and drain regions so as to expose a part of the source and drain regions.

公开(公告)号：US09069202B2

公开(公告)日：2015-06-30

申请号：US13407891

申请日：2012-02-29

申请人： Hidekazu Miyairi ,  Tetsuji Ishitani ,  Daisuke Kubota ,  Toshiyuki Isa ,  Kouhei Toyotaka ,  Susumu Kawashima

发明人： Hidekazu Miyairi ,  Tetsuji Ishitani ,  Daisuke Kubota ,  Toshiyuki Isa ,  Kouhei Toyotaka ,  Susumu Kawashima

IPC分类号： G02F1/1343 ,  G02F1/1333 ,  G02F1/1362 ,  G02F1/136

CPC分类号： G02F1/133345 ,  G02F1/134363 ,  G02F1/136209 ,  G02F1/136213 ,  G02F1/136286 ,  G02F2001/13606 ,  G02F2001/13629 ,  G02F2001/136295 ,  G02F2201/124

摘要： Provided are a liquid crystal display device with horizontal electric field mode, in which a decrease in driving speed can be suppressed by reducing the resistance of a wiring even when the number of pixels is increased, and a manufacturing method thereof. One of a scan wiring and a signal wiring is divided in an intersection portion where the scan wiring and the signal wiring intersect with each other, and the separated wirings are connected with a connection electrode positioned over a thick insulating film. Accordingly, parasitic capacitance at the intersection portion can be reduced, preventing the decrease in the driving speed. The connection electrode is formed at the same time as formation of a pixel electrode and a common electrode using a low-resistance metal, which contributes to the reduction in manufacturing process of the liquid crystal display device.

摘要翻译： 提供一种具有水平电场模式的液晶显示装置及其制造方法，其中即使增加像素数也可以通过降低布线的电阻来抑制驱动速度的降低。 扫描布线和信号布线之一被划分在扫描布线和信号布线彼此相交的交叉部分中，并且分离的布线与位于厚绝缘膜上的连接电极连接。 因此，可以减少交叉部分处的寄生电容，防止驱动速度的降低。 连接电极与使用低电阻金属的像素电极和公共电极的形成同时形成，这有助于液晶显示装置的制造工艺的减少。