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    Fluorinated silicon nitride films
    2.
    发明授权
    Fluorinated silicon nitride films 失效
    氟化氮化硅膜

    公开(公告)号：US5539154A

    公开(公告)日：1996-07-23

    申请号：US429449

    申请日：1995-04-27

    申请人： Son V. Nguyen ,  David M. Dobuzinsky ,  Douglas J. Dopp ,  David L. Harmon

    发明人： Son V. Nguyen ,  David M. Dobuzinsky ,  Douglas J. Dopp ,  David L. Harmon

    IPC分类号： C23C14/06 ,  C23C16/34 ,  C23C16/505 ,  C30B25/02 ,  H01L21/318 ,  H01C7/10

    CPC分类号： C23C16/505 ,  C23C16/345

    摘要： A plasma enhanced chemical vapor deposition process for producing a fluorinated silicon nitride film on a substrate is disclosed. The process utilizes a mixture of silane, perfluorosilane and nitrogen to produce films of high conformality and stability. The silane and perfluorosilane in the mixture are in a ratio of 0.05 to 1 on a volume basis. The preferred silane is SiH.sub.4 and the preferred perfluorosilane is SiF.sub.4. Films prepared by the process are disclosed and their properties are described.

    摘要翻译： 公开了一种用于在衬底上生产氟化氮化硅膜的等离子体增强化学气相沉积工艺。 该方法利用硅烷，全氟硅烷和氮气的混合物来生产具有高共形性和稳定性的薄膜。 混合物中的硅烷和全氟硅烷的体积比为0.05-1。 优选的硅烷是SiH 4，优选的全氟硅烷是SiF 4。 公开了通过该方法制备的膜，并描述了它们的性质。

    Low temperature plasma oxidation process
    4.
    发明授权
    Low temperature plasma oxidation process 失效
    低温等离子体氧化工艺

    公开(公告)号：US5412246A

    公开(公告)日：1995-05-02

    申请号：US186568

    申请日：1994-01-26

    申请人： David M. Dobuzinsky ,  David L. Harmon ,  Srinandan R. Kasi ,  Donald M. Kenney ,  Son V. Nguyen ,  Tue Nguyen ,  Pai-Hung Pan

    发明人： David M. Dobuzinsky ,  David L. Harmon ,  Srinandan R. Kasi ,  Donald M. Kenney ,  Son V. Nguyen ,  Tue Nguyen ,  Pai-Hung Pan

    IPC分类号： C23C8/36 ,  H01L21/31 ,  H01L21/316 ,  H01L21/321 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/12

    CPC分类号： H01L21/32105 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/31662 ,  Y10S148/118 ,  Y10S257/90

    摘要： A process for forming a thin film on a surface of a semiconductor device. The process involves formation of a silicon dioxide film by plasma enhanced thermal oxidation, employing a mixture of ozone and oxygen which are generated separately from the reactor chamber in a volume ratio of about 1-10/1, preferably about 5-7/1, at a temperature generally below 440.degree. C., preferably about 350.degree.-400.degree. C. The process is used to form sidewall oxide spacers on polysilicon gates for field effect transistors. A relatively fast oxidation rate is achieved at a temperature significantly below that employed in conventional oxidation processes, and this serves to reduce dopant diffusion from the polysilicon. In addition, the resulting film demonstrates low stress with good conformal step coverage of the polysilicon gates. Another use of the process is to grow thin gate oxides and oxide-nitride-oxide with a thickness of less than 100 .ANG.. An oxide film of uniform thickness is formed by controlling the temperature, RF power, exposure time and oxygen/ozone ratio for thin gate oxide (

    摘要翻译： 一种在半导体器件的表面上形成薄膜的工艺。 该方法包括通过等离子体增强的热氧化形成二氧化硅膜，采用臭氧和氧的混合物，其以反应器室分开产生，体积比约为1-10 / 1，优选约5-7 / 1， 在一般低于440℃，优选约350-400℃的温度下进行。该方法用于在场效应晶体管的多晶硅栅上形成侧壁氧化物间隔物。 在显着低于常规氧化工艺中使用的温度下实现相对较快的氧化速率，这用于减少掺杂剂从多晶硅的扩散。 此外，所得膜表现出低应力，并具有多晶硅栅极的良好的共形台阶覆盖。 该方法的另一个用途是生长厚度小于100安培的薄栅氧化物和氧化物 - 氮化物 - 氧化物。 通过控制ULSI FET制造中薄栅氧化物（<100 ANGSTROM）应用的温度，RF功率，曝光时间和氧/臭氧比，形成均匀厚度的氧化膜。

    Selective deposition process
    5.
    发明授权
    Selective deposition process 失效
    选择性沉积工艺

    公开(公告)号：US5618379A

    公开(公告)日：1997-04-08

    申请号：US678475

    申请日：1991-04-01

    申请人： Michael D. Armacost ,  Steven A. Grundon ,  David L. Harmon ,  Son V. Nguyen ,  John F. Rembetski

    发明人： Michael D. Armacost ,  Steven A. Grundon ,  David L. Harmon ,  Son V. Nguyen ,  John F. Rembetski

    IPC分类号： B05D7/24 ,  H01L21/3065 ,  H01L21/312 ,  H01L21/762 ,  H01L21/208

    CPC分类号： B05D1/60 ,  H01L21/30655 ,  H01L21/312 ,  H01L21/76232

    摘要： Disclosed is a process for depositing a conformal polymer coating on selected areas of a silicon substrate. The substrate is first exposed through a mask to a gaseous plasma so as to form a film of desired pattern, the plasma comprising a compound having strong electron donating characteristics. Then, the patterned film and the remaining substrate not covered by the film are exposed to the vapor of a monomer, which condenses and polymerizes on the exposed substrate surfaces, but not on the film. The film serves to inhibit substantial deposition of the coating, so as to provide a selective deposition, where the coating is formed only on those areas of the substrate where desired.

    摘要翻译： 公开了一种在硅衬底的选定区域上沉积保形聚合物涂层的方法。 首先将衬底通过掩模暴露于气态等离子体，以形成所需图案的膜，等离子体包含具有强电子给予特性的化合物。 然后，图案化膜和未被膜覆盖的剩余基底暴露于单体的蒸汽，其在暴露的基板表面上而不是在膜上冷凝和聚合。 该膜用于抑制涂层的显着沉积，从而提供选择性沉积，其中仅在需要的基底的那些区域上形成涂层。

    Low temperature plasma oxidation process
    6.
    发明授权
    Low temperature plasma oxidation process 失效
    低温等离子体氧化工艺

    公开(公告)号：US5330935A

    公开(公告)日：1994-07-19

    申请号：US915752

    申请日：1992-07-21

    申请人： David M. Dobuzinsky ,  David L. Harmon ,  Srinandan R Kasi ,  Donald M. Kenney ,  Son Van Nguyen ,  Tue Nguyen ,  Pai-Hung Pan

    发明人： David M. Dobuzinsky ,  David L. Harmon ,  Srinandan R Kasi ,  Donald M. Kenney ,  Son Van Nguyen ,  Tue Nguyen ,  Pai-Hung Pan

    IPC分类号： C23C8/36 ,  H01L21/31 ,  H01L21/316 ,  H01L21/321 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/02

    CPC分类号： H01L21/32105 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/31662 ,  Y10S148/118 ,  Y10S257/90

    摘要： A process for forming a thin film on a surface of a semiconductor device. The process involves formation of a silicon dioxide film by plasma enhanced thermal oxidation, employing a mixture of ozone and oxygen which are generated separately from the reactor chamber in a volume ratio of about 1-10/1, preferably about 5-7/1, at a temperature generally below 440.degree. C., preferably about 350.degree.-400.degree. C. The process is used to form sidewall oxide spacers on polysilicon gates for field effect transistors. A relatively fast oxidation rate is achieved at a temperature significantly below that employed in conventional oxidation processes, and this serves to reduce dopant diffusion from the polysilicon. In addition, the resulting film demonstrates low stress with good conformal step coverage of the polysilicon gates. Another use of the process is to grow thin gate oxides and oxide-nitride-oxide with a thickness of less than 100.ANG.. An oxide film of uniform thickness is formed by controlling the temperature, RF power, exposure time and oxygen/ozone ratio for thin gate oxide (

    摘要翻译： 一种在半导体器件的表面上形成薄膜的工艺。 该方法包括通过等离子体增强的热氧化形成二氧化硅膜，采用臭氧和氧的混合物，其以反应器室分开产生，体积比约为1-10 / 1，优选约5-7 / 1， 在一般低于440℃，优选约350-400℃的温度下进行。该方法用于在场效应晶体管的多晶硅栅上形成侧壁氧化物间隔物。 在显着低于常规氧化工艺中使用的温度下实现相对较快的氧化速率，这用于减少掺杂剂从多晶硅的扩散。 此外，所得膜表现出低应力，并具有多晶硅栅极的良好的共形台阶覆盖。 该方法的另一个用途是生长厚度小于100安培的薄栅氧化物和氧化物 - 氮化物 - 氧化物。 通过控制ULSI FET制造中薄栅氧化物（<100 ANGSTROM）应用的温度，RF功率，曝光时间和氧/臭氧比，形成均匀厚度的氧化膜。

    Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage
    9.
    发明授权
    Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage 有权
    评估SOI设计和结构中充电损害潜力的方法，以消除损坏的可能性

    公开(公告)号：US07132318B2

    公开(公告)日：2006-11-07

    申请号：US11003988

    申请日：2004-12-04

    申请人： Henry A. Bonges, III ,  David L. Harmon ,  Terence B. Hook ,  Wing L. Lai

    发明人： Henry A. Bonges, III ,  David L. Harmon ,  Terence B. Hook ,  Wing L. Lai

    IPC分类号： H01L21/00 ,  H01L21/336 ,  H01L21/8234

    CPC分类号： H01L27/0251

    摘要： Disclosed is a method and structure for altering an integrated circuit design having silicon over insulator (SOI) transistors. The method/structure prevents damage from charging during processing to the gate of SOI transistors by tracing electrical nets in the integrated circuit design, identifying SOI transistors that may have a voltage differential between the source/drain and gate as potentially damaged SOI transistors (based on the tracing of the electrical nets), and connecting a shunt device across the source/drain and the gate of each of the potentially damaged SOI transistors. Alternatively, the method/structure provides for connecting compensating conductors through a series device.

    摘要翻译： 公开了一种用于改变具有绝缘体上硅（SOI）晶体管的集成电路设计的方法和结构。 该方法/结构通过在集成电路设计中跟踪电网来防止在处理到SOI晶体管的栅极期间的充电损坏，识别可能在源极/漏极和栅极之间具有电压差的SOI晶体管作为潜在损坏的SOI晶体管（基于 电网的跟踪），以及在每个潜在损坏的SOI晶体管的源极/漏极和栅极之间连接分流器件。 或者，方法/结构提供通过串联装置连接补偿导体。

    Isolated Zener diode
    10.
    发明授权
    Isolated Zener diode 有权
    隔离齐纳二极管

    公开(公告)号：US08492866B1

    公开(公告)日：2013-07-23

    申请号：US13345881

    申请日：2012-01-09

    申请人： Frederick G. Anderson ,  Natalie B. Feilchenfeld ,  David L. Harmon ,  Richard A. Phelps ,  Yun Shi ,  Michael J. Zierak

    发明人： Frederick G. Anderson ,  Natalie B. Feilchenfeld ,  David L. Harmon ,  Richard A. Phelps ,  Yun Shi ,  Michael J. Zierak

    IPC分类号： H01L29/861 ,  H01L31/107 ,  H01L29/30 ,  H01L29/866 ,  H01L29/34 ,  H01L29/74 ,  H01L31/111 ,  H01L29/73 ,  H01L29/739 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L29/00 ,  H01L29/864

    CPC分类号： H01L29/866 ,  H01L21/76 ,  H01L21/76283 ,  H01L27/0255 ,  H01L29/66106

    摘要： Disclosed is a Zener diode having a scalable reverse-bias breakdown voltage (Vb) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. However, while the anode contact region is contained entirely within the anode well region, one end of the cathode contact region extends laterally into the anode well region. The length of this end can be predetermined in order to selectively adjust the Vb of the diode (e.g., increasing the length reduces Vb of the diode and vice versa). Also disclosed are an integrated circuit, incorporating multiple instances of the diode with different reverse-bias breakdown voltages, a method of forming the diode and a design structure for the diode.

    摘要翻译： 公开了一种齐纳二极管，其具有作为阴极接触区域相对于相邻阴极和阳极阱区域之间的界面的位置的函数的可分级反向偏压击穿电压（Vb）。 具体地，阴极和阳极接触区域被定位成与相应的阴极和阳极阱区域相邻，并进一步被隔离区域分离。 然而，当阳极接触区域完全包含在阳极阱区域内时，阴极接触区域的一端横向延伸到阳极阱区域中。 为了选择性地调节二极管的Vb（例如，增加长度减小二极管的Vb，反之亦然），可以预定该端的长度。 还公开了一种集成电路，其结合具有不同反向偏压击穿电压的二极管的多个实例，形成二极管的方法和二极管的设计结构。