-
公开(公告)号：US20090265028A1
公开(公告)日：2009-10-22
申请号：US12107064
申请日：2008-04-21
申请人： Sri M. Sri-Jayantha , Arun Sharma , Vijayeshwar D. Khanna , Hien P. Dang , David J. Russell , Douglas O. Powell
发明人： Sri M. Sri-Jayantha , Arun Sharma , Vijayeshwar D. Khanna , Hien P. Dang , David J. Russell , Douglas O. Powell
IPC分类号： G06F19/00
CPC分类号： H05K3/0005 , H05K1/0271 , H05K3/4602 , H05K3/4626 , H05K2201/0191 , H05K2201/09136
摘要： A process for large scale production of a laminated organic substrate having reduced thermal warp.
摘要翻译： 用于大规模生产具有降低的热翘曲的层压有机基材的方法。
-
2.发明授权Construction of reliable stacked via in electronic substrates—vertical stiffness control method 有权在电子基板中构建可靠的堆叠通孔 - 垂直刚度控制方法公开(公告)号：US09099458B2
公开(公告)日：2015-08-04
申请号：US13539480
申请日：2012-07-01
IPC分类号： H05K1/11 , H05K1/09 , H01L23/498 , H05K3/46 , H05K1/02
CPC分类号： H01L23/49827 , H01L23/49838 , H01L2224/05001 , H01L2224/05548 , H01L2224/05572 , H01L2224/16 , H01L2924/00014 , H01L2924/15311 , H05K1/0271 , H05K1/116 , H05K3/4602 , H05K2201/0347 , H05K2201/09454 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/0969 , Y10T29/49155 , H01L2224/05599 , H01L2224/05099
摘要： A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing supporting the plurality of stacked vias. The platted through hole landing includes an etched pattern.
摘要翻译： 用于减小垂直刚度的堆叠通孔结构包括：多个堆叠的通孔，每个通孔设置在盘状结构上。 盘状结构包括支撑多个堆叠的通孔的平板通孔平台。 镀层通孔着色包括蚀刻图案。
-
3.发明授权Construction of reliable stacked via in electronic substrates—vertical stiffness control method 有权在电子基板中构建可靠的堆叠通孔 - 垂直刚度控制方法公开(公告)号：US08866026B2
公开(公告)日：2014-10-21
申请号：US13569826
申请日：2012-08-08
IPC分类号： H05K1/11 , H05K1/09 , H05K3/46 , H01L23/498 , H05K1/02
CPC分类号： H01L23/49827 , H01L23/49838 , H01L2224/05001 , H01L2224/05548 , H01L2224/05572 , H01L2224/16 , H01L2924/00014 , H01L2924/15311 , H05K1/0271 , H05K1/116 , H05K3/4602 , H05K2201/0347 , H05K2201/09454 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/0969 , Y10T29/49155 , H01L2224/05599 , H01L2224/05099
摘要： A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing with a thickness of substantially 3 μm. The platted through hole landing includes an etched pattern and a copper top surface.
摘要翻译： 用于减小垂直刚度的堆叠通孔结构包括：多个堆叠的通孔，每个通孔设置在盘状结构上。 盘状结构包括厚度基本为3μm的板状通孔着落。 镀层通孔着色包括蚀刻图案和铜顶表面。
-
公开(公告)号：US20090189290A1
公开(公告)日：2009-07-30
申请号：US12020565
申请日：2008-01-27
CPC分类号： H01L23/49827 , H01L23/498 , H01L23/49838 , H01L2224/05001 , H01L2224/05008 , H01L2224/05572 , H01L2224/16 , H01L2224/16235 , H01L2924/00014 , H01L2924/01078 , H01L2924/10253 , H01L2924/15151 , H01L2924/15311 , H05K1/0222 , H05K1/115 , H05K3/4602 , H05K2201/096 , H05K2201/09609 , Y10T29/49155 , Y10T29/49165 , Y10T29/4919 , Y10T29/49204 , Y10T29/49222 , H01L2224/05599 , H01L2224/05099
摘要： A substrate via structure for stacked vias in a substrate/chip assembly includes: a center via stack and a plurality of stacked vias clustered around the center via stack. In this structure, the center via and the surrounding vias are made of copper. Some of the surrounding vias may be non-functional vias and these may be of a different height than the functional vias.
摘要翻译： 用于衬底/芯片组件中的堆叠通孔的衬底通孔结构包括：中心通孔堆叠和多个堆叠的通孔，围绕中心通过堆叠聚集。 在这种结构中，中心通孔和周围的通孔由铜制成。 一些周围的通孔可以是非功能通孔，并且它们可以具有与功能通孔不同的高度。
-
公开(公告)号：US08242593B2
公开(公告)日：2012-08-14
申请号：US12020565
申请日：2008-01-27
CPC分类号： H01L23/49827 , H01L23/498 , H01L23/49838 , H01L2224/05001 , H01L2224/05008 , H01L2224/05572 , H01L2224/16 , H01L2224/16235 , H01L2924/00014 , H01L2924/01078 , H01L2924/10253 , H01L2924/15151 , H01L2924/15311 , H05K1/0222 , H05K1/115 , H05K3/4602 , H05K2201/096 , H05K2201/09609 , Y10T29/49155 , Y10T29/49165 , Y10T29/4919 , Y10T29/49204 , Y10T29/49222 , H01L2224/05599 , H01L2224/05099
摘要： A substrate via structure for stacked vias in a substrate/chip assembly includes: a center via stack and a plurality of stacked vias clustered around the center via stack. In this structure, the center via and the surrounding vias are made of copper. Some of the surrounding vias may be non-functional vias and these may be of a different height than the functional vias.
摘要翻译： 用于衬底/芯片组件中的堆叠通孔的衬底通孔结构包括：中心通孔堆叠和多个堆叠的通孔，围绕中心通过堆叠聚集。 在这种结构中，中心通孔和周围的通孔由铜制成。 一些周围的通孔可以是非功能通孔，并且它们可以具有与功能通孔不同的高度。
-
公开(公告)号：US08522430B2
公开(公告)日：2013-09-03
申请号：US13549440
申请日：2012-07-14
IPC分类号： H05K3/40 , H01L21/768 , H01L23/48
CPC分类号： H01L23/49827 , H01L23/498 , H01L23/49838 , H01L2224/05001 , H01L2224/05008 , H01L2224/05572 , H01L2224/16 , H01L2224/16235 , H01L2924/00014 , H01L2924/01078 , H01L2924/10253 , H01L2924/15151 , H01L2924/15311 , H05K1/0222 , H05K1/115 , H05K3/4602 , H05K2201/096 , H05K2201/09609 , Y10T29/49155 , Y10T29/49165 , Y10T29/4919 , Y10T29/49204 , Y10T29/49222 , H01L2224/05599 , H01L2224/05099
摘要： A method of fabricating a substrate via structure in a substrate/chip assembly includes steps of: disposing a center via stack for electrical interconnects in the substrate/chip assembly; and providing a plurality of stacked vias surrounding the center via stack. The plurality of stacked vias encircle the center via stack, resulting in no isolated via stacks on the structure. The plurality of stacked vias have both functional and non-functional vias.
摘要翻译： 在衬底/芯片组件中制造衬底通孔结构的方法包括以下步骤：在衬底/芯片组件中布置用于电互连的中心通孔叠层; 以及通过堆叠提供围绕中心的多个堆叠的通孔。 多个堆叠的通孔通过堆叠环绕中心，导致结构上没有隔离的通孔堆叠。 多个堆叠的通孔具有功能和非功能通孔。
-
公开(公告)号：US20120279061A1
公开(公告)日：2012-11-08
申请号：US13549440
申请日：2012-07-14
IPC分类号： H05K3/40
CPC分类号： H01L23/49827 , H01L23/498 , H01L23/49838 , H01L2224/05001 , H01L2224/05008 , H01L2224/05572 , H01L2224/16 , H01L2224/16235 , H01L2924/00014 , H01L2924/01078 , H01L2924/10253 , H01L2924/15151 , H01L2924/15311 , H05K1/0222 , H05K1/115 , H05K3/4602 , H05K2201/096 , H05K2201/09609 , Y10T29/49155 , Y10T29/49165 , Y10T29/4919 , Y10T29/49204 , Y10T29/49222 , H01L2224/05599 , H01L2224/05099
摘要： A method of fabricating a substrate via structure in a substrate/chip assembly includes steps of: disposing a center via stack for electrical interconnects in the substrate/chip assembly; and providing a plurality of stacked vias surrounding the center via stack. The plurality of stacked vias encircle the center via stack, resulting in no isolated via stacks on the structure. The plurality of stacked vias have both functional and non-functional vias.
摘要翻译： 在衬底/芯片组件中制造衬底通孔结构的方法包括以下步骤：在衬底/芯片组件中布置用于电互连的中心通孔叠层; 以及通过堆叠提供围绕中心的多个堆叠的通孔。 多个堆叠的通孔通过堆叠环绕中心，导致结构上没有隔离的通孔堆叠。 多个堆叠的通孔具有功能和非功能通孔。
-
8.发明授权Construction of reliable stacked via in electronic substrates—vertical stiffness control method 有权在电子基板中构建可靠的堆叠通孔 - 垂直刚度控制方法公开(公告)号：US08258410B2
公开(公告)日：2012-09-04
申请号：US12020534
申请日：2008-01-26
CPC分类号： H01L23/49827 , H01L23/49838 , H01L2224/05001 , H01L2224/05548 , H01L2224/05572 , H01L2224/16 , H01L2924/00014 , H01L2924/15311 , H05K1/0271 , H05K1/116 , H05K3/4602 , H05K2201/0347 , H05K2201/09454 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/0969 , Y10T29/49155 , H01L2224/05599 , H01L2224/05099
摘要： A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing supporting the plurality of stacked vias. The platted through hole landing includes a compliant center zone; and spring-like stiffness-reducing connectors for connecting the compliant center zone of the platted through hole landing.
摘要翻译： 用于减小垂直刚度的堆叠通孔结构包括：多个堆叠的通孔，每个通孔设置在盘状结构上。 盘状结构包括支撑多个堆叠的通孔的平板通孔平台。 平板通孔着陆包括顺应中心区域; 以及用于连接板状通孔底板的柔性中心区域的弹簧状刚度减小连接器。
-
9.发明申请EMBEDDED CONSTRAINER DISCS FOR RELIABLE STACKED VIAS IN ELECTRONIC SUBSTRATES 审中-公开用于电子基板中的可靠堆叠VIAS的嵌入式约束盘公开(公告)号：US20090189289A1
公开(公告)日：2009-07-30
申请号：US12020561
申请日：2008-01-27
IPC分类号： H01L23/52 , H01L23/535
CPC分类号： H01L23/49827 , H01L23/49822 , H01L2224/05001 , H01L2224/05008 , H01L2224/05572 , H01L2224/16 , H01L2224/16235 , H01L2924/10253 , H01L2924/15311
摘要： A substrate via structure for stacked vias includes: a plurality of stacked vias, wherein each via is disposed on a landing; and at least one constrainer disc surrounding at least one via, for constraining in-plane deformation of the substrate via structure. The constrainer disc is embedded such that the constrainer disc is disposed between two layers of resin. The constrainer discs may be made of copper. The constrainer disc may be circular or square-shaped. Preferably there is a dielectric gap between the constrainer disc and the via.
摘要翻译： 用于堆叠通孔的衬底通孔结构包括：多个堆叠的通孔，其中每个通孔设置在层站上; 以及围绕至少一个通孔的至少一个约束盘，用于限制基板经由结构的平面内变形。 约束盘被嵌入，使得约束盘设置在两层树脂之间。 约束盘可以由铜制成。 约束盘可以是圆形或正方形。 优选地，在约束盘和通孔之间存在电介质间隙。
-
10.发明申请CONSTRUCTION OF RELIABLE STACKED VIA IN ELECTRONIC SUBSTRATES - VERTICAL STIFFNESS CONTROL METHOD 有权电子基板可靠堆叠构造 - 纵向硬度控制方法公开(公告)号：US20120299195A1
公开(公告)日：2012-11-29
申请号：US13569826
申请日：2012-08-08
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/49827 , H01L23/49838 , H01L2224/05001 , H01L2224/05548 , H01L2224/05572 , H01L2224/16 , H01L2924/00014 , H01L2924/15311 , H05K1/0271 , H05K1/116 , H05K3/4602 , H05K2201/0347 , H05K2201/09454 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/0969 , Y10T29/49155 , H01L2224/05599 , H01L2224/05099
摘要： A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing with a thickness of substantially 3 μm. The platted through hole landing includes an etched pattern and a copper top surface.
摘要翻译： 用于减小垂直刚度的堆叠通孔结构包括：多个堆叠的通孔，每个通孔设置在盘状结构上。 盘状结构包括厚度基本为3μm的板状通孔着落。 镀层通孔着色包括蚀刻图案和铜顶表面。
-
-
-
-
-
-
-
-
-
搜索结果
45 条记录 (耗时 0.03 秒)
