公开(公告)号：US20220189880A1

公开(公告)日：2022-06-16

申请号：US17124352

申请日：2020-12-16

申请人： Srinivas V. Pietambaram ,  Tarek A. Ibrahim ,  Gang Duan ,  Sai Vadlamani ,  Bharat Prasad Penmecha

发明人： Srinivas V. Pietambaram ,  Tarek A. Ibrahim ,  Gang Duan ,  Sai Vadlamani ,  Bharat Prasad Penmecha

IPC分类号： H01L23/538 ,  H01L23/498 ,  H01L25/065

摘要： Disclosed herein are microelectronic structures including glass cores, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a glass core having through-glass vias (TGVs) therein; a metallization region at a first face of the glass core, wherein a conductive pathway in the first metallization region is conductively coupled to at least one of the TGVs; a bridge component in the metallization region; a first conductive contact at a face of the metallization region, wherein the first conductive contact is conductively coupled to the conductive pathway; and a second conductive contact at the face of the metallization region, wherein the second conductive contact is conductively coupled to the bridge component.

公开(公告)号：US10892219B2

公开(公告)日：2021-01-12

申请号：US16305733

申请日：2016-07-01

申请人： Srinivas V. Pietambaram ,  Rahul N. Manepalli

发明人： Srinivas V. Pietambaram ,  Rahul N. Manepalli

IPC分类号： H01L23/522 ,  H01L23/538 ,  H01L21/56 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065

摘要： Disclosed is an embedded multi-die interconnect bridge (EMIB) substrate. The EMIB substrate can comprise an organic substrate, a bridge embedded in the organic substrate and a plurality of routing layers. The plurality of routing layers can be embedded within the bridge. Each routing layer can have a plurality of traces. Each of the plurality of routing layers can have a coefficient of thermal expansion (CTE) that varies from an adjacent routing layer.

公开(公告)号：US20170287860A1

公开(公告)日：2017-10-05

申请号：US15088711

申请日：2016-04-01

申请人： David Unruh ,  Srinivas V. Pietambaram

发明人： David Unruh ,  Srinivas V. Pietambaram

IPC分类号： H01L23/00

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/11464 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1403

摘要： An electroless nickel, electroless palladium, electroless tin stack and associated methods are shown. An example method to form a solder bump may include forming a layer of a second material over a first material at a base of a trench in a solder resist layer. The first material includes nickel and the second material includes palladium. The method further includes depositing a third material that includes tin on the second material using an electroless deposition process, and forming a solder bump out of the third material using a reflow and deflux process.

公开(公告)号：US20080096290A1

公开(公告)日：2008-04-24

申请号：US11584411

申请日：2006-10-19

申请人： Kenneth H. Smith ,  Brian R. Butcher ,  Gregory W. Grynkewich ,  Srinivas V. Pietambaram ,  Nicholas D. Rizzo

发明人： Kenneth H. Smith ,  Brian R. Butcher ,  Gregory W. Grynkewich ,  Srinivas V. Pietambaram ,  Nicholas D. Rizzo

IPC分类号： H01L21/00

CPC分类号： H01L43/12

摘要： Methods and apparatus are provided for magnetoresistive memories employing magnetic tunnel junction (MTJ). The apparatus comprises a MTJ (61, 231), first (60, 220) and second (66, 236) electrodes coupled, respectively, to first (62, 232) and second (64, 234) magnetic layers of the MTJ (61, 231), first (54, 204) and second (92, 260) write conductors magnetically coupled to the MTJ (61, 231) and spaced apart from the first (60, 220) and second (66, 236) electrodes, and at least one etch-stop layer (82, 216) located between the first write conductor (54, 204) and the first electrode (60, 220), having an etch rate in a reagent for etching the MTJ (61, 231) and/or the first electrode (60, 220) that is at most 25% of the etch rate of the MTJ (61, 231) and/or first conductor (60, 220) to the same reagent, so as to allow portions of the MTJ (61, 231) and first electrode (60, 220) to be removed without affecting the underlying first write conductor (54, 204). In a further embodiment, a second etch-stop layer (90, 250) is located between the second electrode (66, 236) and the second write conductor (92, 260). Improved yield and performance are obtained.

摘要翻译： 提供了采用磁隧道结（MTJ）的磁阻存储器的方法和装置。 该装置包括MTJ（61,231），第一（60,220）和第二（66,236）电极，其分别耦合到MTJ（61）的第一（62,232）和第二（64,234）磁性层 ，231），第一（54,204）和第二（92,260）写入导体，其磁耦合到MTJ（61,231）并且与第一（60,220）和第二（66,236）电极间隔开，以及 位于所述第一写入导体（54,204）和所述第一电极（60,220）之间的至少一个蚀刻停止层（82,216）具有用于蚀刻所述MTJ（61,231）的试剂中的蚀刻速率和 /或第一电极（60,220），其至多为MTJ（61,231）和/或第一导体（60,220）的蚀刻速率的25％的相同试剂，以便允许部分 MTJ（61,231）和第一电极（60,220）被去除而不影响下面的第一写入导体（54,204）。 在另一实施例中，第二蚀刻停止层（90,250）位于第二电极（66,236）和第二写入导体（92,260）之间。 获得了提高的产量和性能。

公开(公告)号：US07067331B2

公开(公告)日：2006-06-27

申请号：US10980930

申请日：2004-11-03

申请人： Jon M. Slaughter ,  Renu W. Dave ,  Srinivas V. Pietambaram

发明人： Jon M. Slaughter ,  Renu W. Dave ,  Srinivas V. Pietambaram

IPC分类号： H01L21/00

CPC分类号： B82Y25/00 ,  B82Y10/00 ,  B82Y40/00 ,  G01R33/093 ,  G11B5/3903 ,  G11B5/3909 ,  G11C11/15 ,  H01F10/3204 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/302 ,  H01L43/10 ,  Y10T428/12431

摘要： An amorphous layer of a cobalt iron-based (CoFe-based) magnetic alloy suitable for use in magnetoelectronic devices is disclosed. In the most preferred embodiments of the present invention, at least one amorphous layer is provided in an MTJ stack to increase the smoothness of the various layers in the MTJ stack while also enhancing the magnetic performance of the resulting device. Additionally, the alloys of the present invention are also useful in cladding applications to provide electrical flux containment for signal lines in magnetoelectronic devices and as a material for fabricating write heads.

摘要翻译： 公开了一种适用于磁电子器件的钴铁基（CoFe基）磁性合金的非晶层。 在本发明的最优选实施例中，在MTJ叠层中提供至少一个非晶层，以增加MTJ叠层中各层的平滑度，同时也提高所得装置的磁性能。 此外，本发明的合金还可用于包覆应用中，以提供用于磁电子器件中的信号线的电流容纳以及用作制造写入头的材料。

公开(公告)号：US06541280B2

公开(公告)日：2003-04-01

申请号：US09811656

申请日：2001-03-20

申请人： Vidya S. Kaushik ,  Bich-yen Nguyen ,  Srinivas V. Pietambaram ,  James Kenyon Schaeffer, III

发明人： Vidya S. Kaushik ,  Bich-yen Nguyen ,  Srinivas V. Pietambaram ,  James Kenyon Schaeffer, III

IPC分类号： H01L2100

CPC分类号： H01L21/28194 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28 ,  H01L21/28202 ,  H01L21/28273 ,  H01L28/40 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： A dielectric layer comprises lanthanum, aluminum and oxygen and is formed between two conductors or a conductor and substrate. In one embodiment, the dielectric layer is graded with respect to the lanthanum or aluminum. In another embodiment, an insulating layer is formed between the conductor or substrate and the dielectric layer. The dielectric layer can be formed by atomic layer chemical vapor deposition, physical vapor deposition, organometallic chemical vapor deposition or pulsed laser deposition.

摘要翻译： 介电层包括镧，铝和氧，并且形成在两个导体或导体和衬底之间。 在一个实施例中，电介质层相对于镧或铝分级。 在另一个实施例中，在导体或基底与电介质层之间形成绝缘层。 电介质层可以通过原子层化学气相沉积，物理气相沉积，有机金属化学气相沉积或脉冲激光沉积形成。

公开(公告)号：US10043740B2

公开(公告)日：2018-08-07

申请号：US15208313

申请日：2016-07-12

申请人： Sri Ranga Sai Boyapati ,  Rahul N. Manepalli ,  Dilan Seneviratne ,  Srinivas V. Pietambaram ,  Kristof Darmawikarta ,  Robert Alan May ,  Islam A. Salama

发明人： Sri Ranga Sai Boyapati ,  Rahul N. Manepalli ,  Dilan Seneviratne ,  Srinivas V. Pietambaram ,  Kristof Darmawikarta ,  Robert Alan May ,  Islam A. Salama

IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L21/02 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065

摘要： Semiconductor packages with interconnects having passivation thereon is disclosed. The passivation layer may be any suitable dielectric material that may overlie a build-up dielectric layer and metal traces of an interconnect layer in a semiconductor package. Via holes may be formed in the build-up dielectric and the passivation layer may be removed from the bottom of the via hole. By removing the passivation layer at the bottom of the via hole, any residual build-up dielectric may also be removed from the bottom of the via hole. Thus removal of the residual build-up dielectric may not require a desmear process that would otherwise roughen metal and/or dielectric surfaces. The resulting smoother metal and/or dielectric surfaces enabled by the use of the passivation layer may allow greater process latitude and/or flexibility to fabricate relatively smaller dimensional interconnect features and/or relatively improved signaling frequency and integrity.

公开(公告)号：US07683445B2

公开(公告)日：2010-03-23

申请号：US11740066

申请日：2007-04-25

申请人： Srinivas V. Pietambaram ,  Nicholas D. Rizzo ,  Jon M. Slaughter

发明人： Srinivas V. Pietambaram ,  Nicholas D. Rizzo ,  Jon M. Slaughter

IPC分类号： H01L29/82

CPC分类号： H01L43/08 ,  H01L43/12 ,  Y10S977/838 ,  Y10S977/933

摘要： Low power magnetoelectronic device structures and methods therefore are provided. The magnetoelectronic device structure (100, 150, 450, 451) comprises a programming line (104, 154, 156, 454, 456), a magnetoelectronic device (102, 152, 452) magnetically coupled to the programming line (104, 154, 156, 454, 456), and an enhanced permeability dielectric (EPD) material (106, 108, 110, 158, 160, 162, 458, 460, 462) disposed adjacent the magnetoelectronic device. The EPD material (106, 108, 110, 158, 160, 162, 458, 460, 462) comprises multiple composite layers (408) of magnetic nano-particles (406) embedded in a dielectric matrix (409). The composition of the composite layers is chosen to provide a predetermined permeability profile. A method for making a magnetoelectronic device structure is also provided. The method comprises fabricating the magnetoelectronic device (102, 152, 452) and depositing the programming line (104, 154, 156, 454, 456). The EPD material (106, 108, 110, 158, 160, 162, 458, 460, 462) comprising the multiple composite layers (408) is formed around the magnetoelectronic device (102, 152, 452) and/or between the device (102, 152, 452) and the programming line (104, 154, 156, 454, 456). The presence of the EPD structure (470, 480, 490) in proximity to the programming line (104, 154, 156, 454, 456) and/or the magnetoelectronic device (102, 152, 452) reduces the required programming current.

摘要翻译： 因此提供了低功率磁电子器件结构和方法。 磁电子器件结构（100,150,450,451）包括编程线（104,154,156,454,456），磁耦合到编程线（104,154,452）的磁电子器件（102,152,452） 156,454,456）以及邻近磁电子器件设置的增强磁导率电介质（EPD）材料（106,108,110,158,160,162,458,460,462）。 EPD材料（106,108,110,158,160,162,458,460,462）包括嵌入电介质矩阵（409）中的磁性纳米颗粒（406）的多个复合层（408）。 选择复合层的组成以提供预定的渗透率分布。 还提供了一种制造磁电子器件结构的方法。 该方法包括制造磁电子器件（102,152,452）并沉积编程线（104,154,156,454,456）。 包括多个复合层（408）的EPD材料（106,108,110,158,160,162,458,460,462）形成在磁电子器件（102,152,452）周围和/或在器件（ 102，152,452）和编程线（104,154,156,454,465）。 靠近编程线（104,154,156,454,465）和/或磁电子器件（102,152,452）的EPD结构（470,480,490）的存在减少了所需的编程电流。

公开(公告)号：US07445943B2

公开(公告)日：2008-11-04

申请号：US11584411

申请日：2006-10-19

申请人： Kenneth H. Smith ,  Brian R. Butcher ,  Gregory W. Grynkewich ,  Srinivas V. Pietambaram ,  Nicholas D. Rizzo

发明人： Kenneth H. Smith ,  Brian R. Butcher ,  Gregory W. Grynkewich ,  Srinivas V. Pietambaram ,  Nicholas D. Rizzo

IPC分类号： H01L21/00

CPC分类号： H01L43/12

摘要： Methods and apparatus are provided for magnetoresistive memories employing magnetic tunnel junction (MTJ). The apparatus comprises a MTJ (61, 231), first (60, 220) and second (66, 236) electrodes coupled, respectively, to first (62, 232) and second (64, 234) magnetic layers of the MTJ (61, 231), first (54, 204) and second (92, 260) write conductors magnetically coupled to the MTJ (61, 231) and spaced apart from the first (60, 220) and second (66, 236) electrodes, and at least one etch-stop layer (82, 216) located between the first write conductor (54, 204) and the first electrode (60, 220), having an etch rate in a reagent for etching the MTJ (61, 231) and/or the first electrode (60, 220) that is at most 25% of the etch rate of the MTJ (61, 231) and/or first conductor (60, 220) to the same reagent, so as to allow portions of the MTJ (61, 231) and first electrode (60, 220) to be removed without affecting the underlying first write conductor (54, 204). In a further embodiment, a second etch-stop layer (90, 250) is located between the second electrode (66, 236) and the second write conductor (92, 260). Improved yield and performance are obtained.

摘要翻译： 提供了采用磁隧道结（MTJ）的磁阻存储器的方法和装置。 该装置包括MTJ（61,231），第一（60,220）和第二（66,236）电极，其分别耦合到MTJ（61）的第一（62,232）和第二（64,234）磁性层 ，231），第一（54,204）和第二（92,260）写入导体，其磁耦合到MTJ（61,231）并且与第一（60,220）和第二（66,236）电极间隔开，以及 位于所述第一写入导体（54,204）和所述第一电极（60,220）之间的至少一个蚀刻停止层（82,216）具有用于蚀刻所述MTJ（61,231）的试剂中的蚀刻速率和 /或第一电极（60,220），其至多为MTJ（61,231）和/或第一导体（60,220）的蚀刻速率的25％的相同试剂，以便允许部分 MTJ（61,231）和第一电极（60,220）被去除而不影响下面的第一写入导体（54,204）。 在另一实施例中，第二蚀刻停止层（90,250）位于第二电极（66,236）和第二写入导体（92,260）之间。 获得了提高的产量和性能。

公开(公告)号：US20070278547A1

公开(公告)日：2007-12-06

申请号：US11444089

申请日：2006-05-31

申请人： Srinivas V. Pietambaram ,  Bengt J. Akerman ,  Renu W. Dave ,  Jason A. Janesky ,  Nicholas D. Rizzo ,  Jon M. Slaughter

发明人： Srinivas V. Pietambaram ,  Bengt J. Akerman ,  Renu W. Dave ,  Jason A. Janesky ,  Nicholas D. Rizzo ,  Jon M. Slaughter

IPC分类号： H01L29/94

CPC分类号： H01L43/08 ,  G11C11/161 ,  H01L27/222 ,  H01L43/02 ,  H01L43/10

摘要： An MRAM bit (10) includes a free magnetic region (15), a fixed magnetic region (17) comprising an antiferromagnetic material, and a tunneling barrier (16) comprising a dielectric layer positioned between the free magnetic region (15) and the fixed magnetic region (17). The MRAM bit (10) avoids a pinning layer by comprising a fixed magnetic region exhibiting a well-defined high Hflop using a combination of high Hk (uniaxial anisotropy), high Hsat (saturation field), and ideal soft magnetic properties exhibiting well-defined easy and hard axes.

摘要翻译： MRAM位（10）包括自由磁区（15），包括反铁磁材料的固定磁区（17）和隧道势垒（16），其包括位于自由磁区（15）和固定 磁区（17）。 MRAM位（10）通过使用高H H k（单轴各向异性）的组合，包括表现出明确定义的高电平触发器的固定磁场来避免钉扎层， 高饱和场（饱和磁场），理想的软磁特性表现出明确的容易和硬轴。