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    Phase detector for carrier recovery in a DQPSK receiver
    1.
    发明授权
    Phase detector for carrier recovery in a DQPSK receiver 失效
    DQPSK接收机载波恢复的相位检测器

    公开(公告)号：US06097768A

    公开(公告)日：2000-08-01

    申请号：US968202

    申请日：1997-11-12

    申请人： Stephen T. Janesch ,  Alan F. Hendrickson ,  Paul G. Schnizlein

    发明人： Stephen T. Janesch ,  Alan F. Hendrickson ,  Paul G. Schnizlein

    IPC分类号： G06F11/00 ,  H03L7/093 ,  H03L7/099 ,  H03L7/107 ,  H03L7/14 ,  H03M13/00 ,  H04B1/707 ,  H04L1/24 ,  H04L7/033 ,  H04L27/00 ,  H04L27/22 ,  H04L27/227 ,  H03D3/22

    CPC分类号： H04L27/2275 ,  H03L7/0991 ,  H03L7/107 ,  H03L7/146 ,  H04B1/707 ,  H04L1/24 ,  H04L27/22 ,  H04L27/2273 ,  H04L27/2277 ,  H03L7/093 ,  H04L2027/0028 ,  H04L2027/0046 ,  H04L2027/0067 ,  H04L2027/0069 ,  H04L7/0334

    摘要： A phase detector using simple arithmetic operations to measure phase errors in the carrier-recovery mechanism for a DQPSK digital communications receiver. The carrier-recovery mechanism is a feedback loop that provides a synchronization between the oscillators in the transmitter and receiver of the communications system; the phase detector measures deviations from this synchronization and generates a phase-error signal used in the feedback loop to synchronize the oscillators. To perform this measurement, the phase detector takes the received signal as input and compares it against a local oscillator in the receiver to generate two digital signals: the in-phase (I) and quadrature-phase (Q) components of the received signal. These signals are the input to a logic unit, which uses these two signals to determine the phase-error signal. In one embodiment of the phase detector, the logic unit analyzes the signs of the two digital signals and then accordingly adds or subtracts the I and Q signals to generate the phase-error signal. In another embodiment, the logic unit determines the magnitude of the phase-error signal by finding the difference in magnitudes of the two digital signals and constructing a phase-error signal proportional to this difference. The logic unit then determines the sign of the phase-error signal by analyzing the signs of the I and Q digital signals. The logic unit thus uses simple arithmetic operations to generate the phase-error signal, thereby reducing the complexity and cost of the phase detector.

    摘要翻译： 一种相位检测器，使用简单的算术运算来测量DQPSK数字通信接收机的载波恢复机制中的相位误差。 载波恢复机制是提供通信系统的发射机和接收机中的振荡器之间的同步的反馈回路; 相位检测器测量与该同步的偏差，并产生在反馈环路中使用的相位误差信号以使振荡器同步。 为了执行该测量，相位检测器将接收的信号作为输入，并将其与接收机中的本地振荡器进行比较以产生两个数字信号：接收信号的同相（I）和正交相（Q）分量。 这些信号是逻辑单元的输入，它使用这两个信号来确定相位误差信号。 在相位检测器的一个实施例中，逻辑单元分析两个数字信号的符号，然后相应地增加或减去I和Q信号以产生相位误差信号。 在另一个实施例中，逻辑单元通过找到两个数字信号的幅度差异来构造相位误差信号的大小，并且构成与该差成比例的相位误差信号。 逻辑单元然后通过分析I和Q数字信号的符号来确定相位误差信号的符号。 因此，逻辑单元使用简单的算术运算来产生相位误差信号，从而降低了相位检测器的复杂性和成本。

    Carrier-recovery loop with stored initialization in a radio receiver
    2.
    发明授权
    Carrier-recovery loop with stored initialization in a radio receiver 失效
    在无线电接收机中存储初始化的载波恢复循环

    公开(公告)号：US6072842A

    公开(公告)日：2000-06-06

    申请号：US968029

    申请日：1997-11-12

    申请人： Stephen T. Janesch ,  Paul G. Schnizlein ,  Ed Bell

    发明人： Stephen T. Janesch ,  Paul G. Schnizlein ,  Ed Bell

    IPC分类号： H03L7/093 ,  H03L7/099 ,  H03L7/14 ,  H04L1/24 ,  H04L7/033 ,  H04L27/00 ,  H04L27/22 ,  H04L27/227 ,  H03D3/24

    CPC分类号： H04L27/22 ,  H03L7/0991 ,  H03L7/146 ,  H04L1/24 ,  H04L27/2273 ,  H03L7/093 ,  H04L2027/0028 ,  H04L2027/0046 ,  H04L2027/0067 ,  H04L2027/0069 ,  H04L7/0334

    摘要： A carrier-recovery loop for a receiver in a communication system with features that facilitate initialization of the loop. The carrier-recovery loop is a PLL that uses a feedback signal to keep a recovery oscillator phase-locked to the carrier of a received signal. In the present invention, an initializing value of the feedback signal is stored in a memory and provided to a digitally controlled recovery oscillator (DCO). This initializing value brings the recovered signal to an initial frequency that approximates the carrier frequency. When the receivers starts to acquire a phase-lock with the carrier, the carrier-recovery loop is in a condition close to the desired phase lock. Preparing the DCO in this manner imparts a significant improvement to the carrier-recovery loop. The response time for the loop to acquire a phase lock depends in part on its initial frequency offset from the carrier. In general, reducing this initial offset reduces the loop's acquisition time. By thus anticipating the frequency of the carrier, this carrier-recovery loop can have an improved acquisition time to reach phase lock. The initializing value of the feedback signal can be generated by recording a sample of the feedback signal when the carrier-recovery loop is phase-locked to a received signal or to an on-board crystal oscillator. The invention also includes a mechanism to correct drifts in the crystal oscillator's frequency.

    摘要翻译： 具有促进循环初始化的特征的通信系统中的接收机的载波恢复回路。 载波恢复环路是使用反馈信号将恢复振荡器锁相到接收信号的载波的PLL。 在本发明中，将反馈信号的初始化值存储在存储器中并提供给数字控制的恢复振荡器（DCO）。 该初始化值使恢复的信号达到近似载波频率的初始频率。 当接收机开始与载波采集相位锁定时，载波恢复环路处于接近所需相位锁定状态。 以这种方式准备DCO对载体恢复循环有显着的改进。 环路获取锁相的响应时间部分取决于其与载波的初始频率偏移。 一般来说，减少初始偏移可以减少环路的采集时间。 通过这样预期载波的频率，该载波恢复回路可以具有改善的采集时间以达到锁相。 反馈信号的初始化值可以通过当载波恢复环路锁相到接收信号时记录反馈信号的样本，或者通过在板上晶体振荡器上记录反馈信号的初始化值。 本发明还包括校正晶体振荡器频率漂移的机制。

    Configurable input buffer dependent on supply voltage
    3.
    发明授权
    Configurable input buffer dependent on supply voltage 失效
    可配置的输入缓冲器取决于电源电压

    公开(公告)号：US5477172A

    公开(公告)日：1995-12-19

    申请号：US354337

    申请日：1994-12-12

    申请人： Paul G. Schnizlein

    发明人： Paul G. Schnizlein

    IPC分类号： H03K19/00 ,  H03K19/003 ,  H03K17/693

    CPC分类号： H03K19/0016

    摘要： An input buffer is described which is configurable depending on whether a 5.0 or 3.3 volt supply voltage is present, The input buffer includes two input buffer circuits. The output of a first input buffer circuit is output as valid data when the supply voltage VCC equals 5.0 volts. The output of the second input buffer circuit is output as valid data when the supply voltage VCC equals 3.3 volts.

    摘要翻译： 描述了根据是否存在5.0或3.3伏电源电压来配置的输入缓冲器。输入缓冲器包括两个输入缓冲器电路。 当电源电压VCC等于5.0伏时，第一输入缓冲电路的输出作为有效数据输出。 当电源电压VCC等于3.3V时，第二输入缓冲电路的输出作为有效数据输出。

    Clock switcher circuit
    4.
    发明授权
    Clock switcher circuit 失效
    时钟切换电路

    公开(公告)号：US5502409A

    公开(公告)日：1996-03-26

    申请号：US364436

    申请日：1994-12-27

    申请人： Paul G. Schnizlein ,  David E. Norris

    发明人： Paul G. Schnizlein ,  David E. Norris

    IPC分类号： G06F1/06 ,  G06F1/08 ,  H03K5/00 ,  H03K17/00 ,  H03K5/13

    CPC分类号： G06F1/08

    摘要： A clock switcher circuit for providing at least one set of clock signals selected from a plurality of clock sources. A first clock signal having a first pulse length and a second clock signal having a second pulse length are circuit inputs. Another circuit input is a clock selection input. When the clock selection input indicates a new output clock signal, different from the then current output clock signal, should be output by the circuit, the circuit provides a means for switching to output the new output clock signal. In switching to output the new output clock signal, the circuit prevents the occurrence of the output clock signal ever having a pulse shorter than the normal pulse length of the then current output clock signal, whether the then current output clock signal is the first clock signal or the second clock signal.

    摘要翻译： 一种用于提供从多个时钟源中选择的至少一组时钟信号的时钟切换器电路。 具有第一脉冲长度的第一时钟信号和具有第二脉冲长度的第二时钟信号是电路输入。 另一个电路输入是时钟选择输入。 当时钟选择输入指示新的输出时钟信号，与当前输出时钟信号不同时，应由电路输出，该电路提供切换输出新输出时钟信号的手段。 在切换输出新的输出时钟信号时，电路防止输出时钟信号的出现持续时间短于当前输出时钟信号的正常脉冲长度，无论当前的输出时钟信号是否为第一个时钟信号 或第二时钟信号。

    CMOS D-type flip-flop circuits
    5.
    发明授权
    CMOS D-type flip-flop circuits 失效
    CMOS D型触发器电路

    公开(公告)号：US4691122A

    公开(公告)日：1987-09-01

    申请号：US717350

    申请日：1985-03-29

    申请人： Paul G. Schnizlein ,  Wen-Tsung F. Tang

    发明人： Paul G. Schnizlein ,  Wen-Tsung F. Tang

    IPC分类号： H01L27/11 ,  G11C11/41 ,  G11C19/28 ,  H01L21/8244 ,  H01L27/10 ,  H03K3/037 ,  H03K3/356 ,  H03K3/3562 ,  H03K3/26 ,  H03K3/284 ,  H03K17/16 ,  H03K19/096

    CPC分类号： H03K3/356104 ,  G11C19/28 ,  H03K3/3562

    摘要： A CMOS D-type flip-flop circuit stage for avoiding the possibilty of feedthrough includes a non-overlapping clock generator section having a true clock output and a complement clock output. The flip-flop circuit includes a master section formed of a first transfer gate, a first regenerative transistor and a first inverter gate. The flip-flop circuit further includes a slave section formed of a second transfer gate, a second regenerative transistor and a second inverter gate. The clock generator provides a two-phase non-overlapping clock for clocking both the master and slave sections so as to prevent inadvertent racethrough of data input to successive stages.

    摘要翻译： 用于避免馈通的可能性的CMOS D型触发器电路级包括具有真实时钟输出和补码时钟输出的非重叠时钟发生器部分。 触发器电路包括由第一传输栅极，第一再生晶体管和第一反相器栅极形成的主部分。 触发器电路还包括由第二传输栅极，第二再生晶体管和第二反相器栅极形成的从部分。 时钟发生器提供两相不重叠的时钟，用于对主部分和从部分进行计时，以防止数据输入到连续阶段的无意中的穿通。

    Power supply dependent method of controlling a charge pump
    8.
    发明授权
    Power supply dependent method of controlling a charge pump 失效
    电源依赖的控制电荷泵的方法

    公开(公告)号：US5537077A

    公开(公告)日：1996-07-16

    申请号：US511421

    申请日：1995-08-04

    申请人： Paul G. Schnizlein

    发明人： Paul G. Schnizlein

    IPC分类号： G01R19/165 ,  G05F3/30 ,  G10H1/18 ,  G10H7/02 ,  H03K19/00 ,  H03K19/0175 ,  H03L5/00

    CPC分类号： G10H7/02 ,  G10H1/186

    摘要： A supply voltage detect circuit is described which generates a control signal indicating the status of VCC to be at 5.0 or 3.3 volts. This control signal is used to generate analog reference signals used by A/D and/or D/A circuitry in an audio processing integrated circuit and by other circuitry to control clock frequencies or current drive.

    摘要翻译： 描述了一种电源电压检测电路，其生成指示VCC的状态为5.0或3.3伏的控制信号。 该控制信号用于产生由音频处理集成电路中的A / D和/或D / A电路使用的模拟参考信号，以及用于控制时钟频率或电流驱动的其它电路。

    Keypad scanning with few pins
    9.
    发明授权
    Keypad scanning with few pins 有权
    小键盘扫描

    公开(公告)号：US06424274B1

    公开(公告)日：2002-07-23

    申请号：US09290139

    申请日：1999-04-13

    申请人： Paul G. Schnizlein ,  Kenneth Tallo

    发明人： Paul G. Schnizlein ,  Kenneth Tallo

    IPC分类号： H03K1794

    CPC分类号： H03M11/24

    摘要： The invention is, in its various aspects, an apparatus and a method for scanning a keypad or a keyboard. The apparatus comprises a keypad and an integrated circuit. The keypad includes a plurality of chained resistors and a plurality of key switches. Each of the plurality of key switches is tied to a common node at a first terminal thereof and tapping the chained resistors at a second node thereof. Each of the key switches generates a signal indicative of the respective key switch being pressed when the key switch is pressed. The integrated circuit is capable of receiving the generated signal. The integrated circuit furthermore includes an analog to digital converter capable of generating a reference signal and a circuit capable of determining which key switch has been pressed from the magnitude of the generated voltage signal and the reference signal. The method for scanning a keypad comprises generating a voltage signal whose magnitude indicates which key is being pressed, and determining from the magnitude of the generated voltage signal which key was pressed.

    摘要翻译： 本发明在其各个方面是用于扫描小键盘或键盘的装置和方法。 该装置包括键盘和集成电路。 键盘包括多个链式电阻器和多个键开关。 多个键开关中的每一个在其第一端处被连接到公共节点，并在其第二节点敲击链接的电阻器。 当按键开关被按下时，每个按键开关产生指示按压各个按键开关的信号。 集成电路能够接收所产生的信号。 集成电路还包括能够产生参考信号的模/数转换器和能够根据产生的电压信号和参考信号的大小来确定哪个键开关被按下的电路。 用于扫描键盘的方法包括产生一个电压信号，该电压信号的幅度指示正在按下哪个键，并根据产生的电压信号的大小来确定哪一个键被按下。

    Training preamble added to CT2 muxes in a CT2 wireless telecommunications system
    10.
    发明授权
    Training preamble added to CT2 muxes in a CT2 wireless telecommunications system 失效
    在CT2无线电信系统中增加了CT2多路复用器的培训前言

    公开(公告)号：US06259709B1

    公开(公告)日：2001-07-10

    申请号：US08850852

    申请日：1997-05-02

    申请人： Paul G. Schnizlein ,  Javier V. Magana ,  James J. Covell

    发明人： Paul G. Schnizlein ,  Javier V. Magana ,  James J. Covell

    IPC分类号： H04J306

    CPC分类号： H04L7/041

    摘要： Described herein is a system and method of disabling D bits in a CT2 MUX signaling channel. When the bit count equals the bit location of where the D bits are typically located in the signaling channel of a CT2 MUX, circuitry of the present invention disables a D bit enable signal from being processed. The D bit enable signal would typically allow a transmitter and receiver to, respectively, send a bit as a D bit, or process a received bit as a D bit. The suffix of the CT2 MUX, consisting of D bits, is unaffected by the present invention.

    摘要翻译： 这里描述的是禁止CT2 MUX信令信道中的D比特的系统和方法。 当位计数等于D位通常位于CT2 MUX的信令信道中的位位置时，本发明的电路禁止D位使能信号被处理。 D位使能信号通常允许发送器和接收器分别将位作为D位发送，或将接收的位处理为D位。 由D位组成的CT2 MUX的后缀不受本发明的影响。