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1.发明授权Chemical-mechanical polishing slurry formulation and method for tungsten and titanium thin films 失效化学机械抛光浆料配方及钨钛薄膜的制备方法
公开(公告)号：US5916855A
公开(公告)日：1999-06-29
申请号：US829704
申请日：1997-03-26
IPC分类号： C09G1/02 , C09K3/14 , H01L21/321 , H01L21/3105 , H01L21/306
CPC分类号： C09G1/02 , C09K3/1463 , H01L21/3212
摘要： A polishing slurry composition and its method of making for planarization of silicon semiconductor wafers by chemical mechanical polishing of the wafer. A slurry formulation utilizing a ferric salt tungsten oxidizer, an ammonium persulfate titanium oxidizer, a fatty acid suspension agent, alumina particles with a small diameter and tight diameter range, coated with a solubility coating, and a chemical stabilizer, provides high tungsten and titanium polish rates with high selectivity to silicon dioxide, and good oxide defectivity for use in tungsten local interconnect applications. A method for making a tungsten slurry includes first thoroughly blending small diameter alumina particles with a tight diameter range in an aqueous concentrate with a suspension agent, then mixing with water and oxidizers. Ferric salt tungsten slurries made by this method provide excellent tungsten polish characteristics for via plug and local interconnect applications.
摘要翻译： 抛光浆料组合物及其通过晶片的化学机械抛光来制造硅半导体晶片的平面化的方法。 使用三价铁钨氧化剂，过硫酸铵钛氧化剂，脂肪酸悬浮剂，小直径和紧密直径范围的氧化铝颗粒，涂覆有溶解度涂层和化学稳定剂的浆料配方提供高钨和钛抛光 对二氧化硅具有高选择性的速率，以及用于钨局部互连应用的良好的氧化物缺陷率。 一种制备钨浆料的方法包括首先用具有悬浮剂的含水浓缩物中将紧密直径范围的小直径氧化铝颗粒充分混合，然后与水和氧化剂混合。 通过该方法制备的铁盐钨浆通过插塞和局部互连应用提供优异的钨酸盐抛光特性。
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公开(公告)号：US06657304B1
公开(公告)日：2003-12-02
申请号：US10165510
申请日：2002-06-06
IPC分类号： H01L2352
CPC分类号： H01L21/76843 , H01L21/32051 , H01L21/76826 , H01L21/76829 , H01L21/76831 , H01L21/76871 , H01L21/76876 , H01L2221/1089
摘要： A manufacturing method, and an integrated circuit resulting therefrom, has a substrate and a semiconductor device thereon. A stop layer over the substrate has a first dielectric layer formed thereon having an opening into which a first conformal barrier is formed. A first conformal barrier liner is formed in the opening, processed, and treated to improve adhesion. Portions of the first conformal barrier liner on the sidewalls act as a barrier to diffusion of conductor core material to the first dielectric layer. A conductor material is formed in the opening over the vertical portions of the first conformal barrier liner and the first stop layer.
摘要翻译： 一种制造方法和由此产生的集成电路在其上具有基板和半导体器件。 衬底上的停止层具有形成在其上的第一电介质层，其上形成有第一共形势垒的开口。 在开口中形成第一共形阻挡衬里，加工和处理以改善粘附性。 侧壁上的第一共形阻挡衬里的部分作为导体芯材料扩散到第一介电层的障碍。 导体材料形成在第一共形阻挡衬里和第一止挡层的垂直部分上的开口中。
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公开(公告)号：US06525428B1
公开(公告)日：2003-02-25
申请号：US10183458
申请日：2002-06-28
IPC分类号： H01L2348
CPC分类号： H01L21/76832 , H01L21/76807 , H01L23/5222 , H01L23/53228 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , Y10S438/931 , H01L2924/00
摘要： Improved etch selectivity, barrier metal wetting and reduced interconnect capacitance are achieved by implementing damascene processing employing a graded middle etch stop layer comprising a first silicon carbide layer, a silicon-rich layer on the first silicon carbide, and a second silicon carbide layer on the silicon-rich layer. Embodiments include sequentially depositing a porous low-k dielectric layer over a lower capped Cu line, depositing the graded middle-etch stop layer, depositing a porous low-k dielectric layer on the graded middle-etch stop layer, forming a dual damascene opening exposing the silicon-rich surface at the bottom of the trench opening, depositing a seed layer, depositing a barrier middle layer, such as Ta or a Ta/TaN composite, and filling the opening with Cu.
摘要翻译： 改进的蚀刻选择性，阻挡金属润湿和降低的互连电容通过实施使用包括第一碳化硅层，第一碳化硅上的富硅层和第二碳化硅层上的第二碳化硅层的分级中间蚀刻停止层的镶嵌加工来实现 富硅层。 实施例包括在下部封装的Cu线上顺序沉积多孔低k电介质层，沉积渐变的中间蚀刻停止层，在分级中间蚀刻停止层上沉积多孔低k电介质层，形成双镶嵌开口露出 在沟槽开口的底部的富硅表面，沉积种子层，沉积阻挡中间层，如Ta或Ta / TaN复合材料，并用Cu填充开口。
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公开(公告)号：US07157795B1
公开(公告)日：2007-01-02
申请号：US10934511
申请日：2004-09-07
IPC分类号： H01L23/48
CPC分类号： H01L21/2855 , H01L21/76843 , H01L21/76846 , H01L21/76849 , Y10S438/927
摘要： Electromigration and stress migration of Cu interconnects are significantly reduced by forming a composite capping layer comprising a layer of tantalum nitride on the upper surface of the inlaid Cu and a layer of α-Ta on the titanium nitride layer. Embodiments include forming a recess in an upper surface of an upper surface of Cu inlaid in a dielectric layer, depositing a layer of titanium nitride of a thickness of 20 Å to 100 Å and then depositing a layer of α-Ta at a thickness of 200 Å to 500 Å.
摘要翻译： 通过在镶嵌Cu的上表面上形成包含氮化钽层的复合顶盖层和氮化钛层上的α-Ta层，显着降低了铜互连的电迁移和应力迁移。 实施例包括在介电层中嵌入的Cu的上表面的上表面中形成凹陷，沉积厚度为的厚度为的二氧化钛层，然后沉积厚度为200埃的α-Ta层 Å至500Å。
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公开(公告)号：US06836017B2
公开(公告)日：2004-12-28
申请号：US10759170
申请日：2004-01-20
申请人： Minh Van Ngo , Christy Mei-Chu Woo , Steven C. Avanzino , John E. Sanchez, Jr. , Suzette K. Pangrle
发明人： Minh Van Ngo , Christy Mei-Chu Woo , Steven C. Avanzino , John E. Sanchez, Jr. , Suzette K. Pangrle
IPC分类号： H01L2348
CPC分类号： H01L21/76831 , H01L21/76807
摘要： Low-k ILDs are protected from degradation during damascene processing by depositing a thin, conformal silicon carbide liner with a silicon-rich surface before barrier metal layer deposition. Embodiments include forming a dual damascene opening in porous low-k dielectric layers, depositing a thin silicon carbide liner with a silicon-rich surface lining the opening, depositing a barrier metal layer, such as a Ta/TaN composite, and filling the opening with Cu.
摘要翻译： 通过在阻挡金属层沉积之前沉积具有富硅表面的薄的，保形的碳化硅衬垫，可以防止在大马士革加工过程中低k ILD降解。 实施例包括在多孔低k电介质层中形成双镶嵌开口，沉积具有衬在开口上的富硅表面的薄碳化硅衬垫，沉积阻挡金属层，例如Ta / TaN复合材料，并用 铜。
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6.发明授权Point of use mixing for LI/plug tungsten polishing slurry to improve existing slurry 失效使用点混合为LI /塞钨抛光浆料改善现有浆料
公开(公告)号：US6017463A
公开(公告)日：2000-01-25
申请号：US976026
申请日：1997-11-21
CPC分类号： B24B37/044 , C09G1/02 , C09K3/1409 , C09K3/1463 , H01L21/3212 , H01L21/76895 , H01L23/53257 , H01L2924/0002
摘要： An improved tungsten plug/Local Interconnect slurry for Chemical Mechanical Polishing which does not require inclusion of a chemical stabilizer. The slurry is made using a combination of two separate batch mixings of stable ingredients and Point-of Use mixing of portions of the two batches, whereby the oxidizers are combined with the coated abrasive mixture immediately prior to dispensing the slurry onto the polishing pad by combining selected flows from each of the two batches to form a total flow rate equal to the required rate of slurry flow onto the polishing pad.
摘要翻译： 用于化学机械抛光的改进的钨丝塞/局部互连浆料，不需要包含化学稳定剂。 浆料是使用两种分批的混合批料混合物的组合制成的，其中两批分批混合的两批次的部分混合，由此在将浆料分配到抛光垫上之前将氧化剂与涂覆的磨料混合物组合 从两个批次中的每一个选择的流量形成等于浆料流入抛光垫的所需速率的总流量。
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公开(公告)号：US06989604B1
公开(公告)日：2006-01-24
申请号：US10672103
申请日：2003-09-26
IPC分类号： H01L23/52
CPC分类号： H01L21/76843 , H01L21/32051 , H01L21/76826 , H01L21/76829 , H01L21/76831 , H01L21/76871 , H01L21/76876 , H01L2221/1089
摘要： An integrated circuit having a substrate and a semiconductor device thereon. A stop layer over the substrate has a first dielectric layer formed thereon having an opening into which a first conformal barrier is formed. A first conformal barrier liner is formed in the opening, processed, and treated to improve adhesion. Portions of the first conformal barrier liner on the sidewalls act as a barrier to diffusion of conductor core material to the first dielectric layer. A conductor material is formed in the opening over the vertical portions of the first conformal barrier liner and the first stop layer.
摘要翻译： 一种在其上具有基板和半导体器件的集成电路。 衬底上的停止层具有形成在其上的第一电介质层，其上形成有第一共形势垒的开口。 在开口中形成第一共形阻挡衬里，加工和处理以改善粘附性。 侧壁上的第一共形阻挡衬里的部分作为导体芯材料扩散到第一介电层的障碍。 导体材料形成在第一共形阻挡衬里和第一止挡层的垂直部分上的开口中。
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公开(公告)号：US06723635B1
公开(公告)日：2004-04-20
申请号：US10115245
申请日：2002-04-04
申请人： Minh Van Ngo , Christy Mei-Chu Woo , Steven C. Avanzino , John E. Sanchez, Jr. , Suzette K. Pangrle
发明人： Minh Van Ngo , Christy Mei-Chu Woo , Steven C. Avanzino , John E. Sanchez, Jr. , Suzette K. Pangrle
IPC分类号： H01L214763
CPC分类号： H01L21/76831 , H01L21/76807
摘要： Low-k ILDs are protected from degradation during damascene processing by depositing a thin, conformal silicon carbide liner with a silicon-rich surface before barrier metal layer deposition. Embodiments include forming a dual damascene opening in porous low-k dielectric layers, depositing a thin silicon carbide liner with a silicon-rich surface lining the opening, depositing a barrier metal layer, such as a Ta/TaN composite, and filling the opening with Cu.
摘要翻译： 通过在阻挡金属层沉积之前沉积具有富硅表面的薄的，保形的碳化硅衬垫，可以防止在大马士革加工过程中低k ILD降解。 实施例包括在多孔低k电介质层中形成双镶嵌开口，沉积具有衬在开口上的富硅表面的薄碳化硅衬垫，沉积阻挡金属层，例如Ta / TaN复合材料，并用 铜。
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公开(公告)号：US06806172B1
公开(公告)日：2004-10-19
申请号：US09826078
申请日：2001-04-05
申请人： Christy Mei-Chu Woo , Eric N. Paton , Susan Tover
发明人： Christy Mei-Chu Woo , Eric N. Paton , Susan Tover
IPC分类号： H01L21425
CPC分类号： H01L29/665 , H01L21/324 , H01L29/7833
摘要： Nickel film formation is implemented by heating a deposition chamber during deposition of nickel on a substrate or between processing of two or more substrates or both. Embodiments include forming a nickel silicide on a composite having an exposed silicon surface by introducing the substrate to a PVD chamber having at least one heating element for heating the chamber and depositing a layer of nickel directly on the exposed silicon surface of the composite while concurrently heating the chamber with the heating element.
摘要翻译： 通过在将镍沉积在基底上或在两个或更多个基底或两者的处理之间加热沉积室来实现镍膜形成。 实施例包括在具有暴露的硅表面的复合材料上形成硅化镍，通过将衬底引入具有至少一个用于加热室的加热元件的PVD室，并将镍层直接沉积在复合材料的暴露的硅表面上，同时加热 具有加热元件的室。
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公开(公告)号：US06661067B1
公开(公告)日：2003-12-09
申请号：US10260514
申请日：2002-10-01
IPC分类号： H01L2994
CPC分类号： H01L29/665 , H01L21/3115 , Y10S257/90
摘要： Bridging between nickel suicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a nitrogen plasma to create a surface region having reduced free silicon. Embodiments include treating the silicon nitride sidewall spacers with a nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.
摘要翻译： 通过用氮等离子体处理氮化硅侧壁间隔物的暴露表面来形成具有减少的游离硅的表面区域，防止栅电极上的硅化镍层与沿着氮化硅侧壁间隔物的源/漏区之间的桥接。 实施例包括用氮等离子体处理氮化硅侧壁间隔物以将表面区域的折射率降低到小于约1.95。
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