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    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
    6.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE 有权
    三维半导体器件

    公开(公告)号：US20140183756A1

    公开(公告)日：2014-07-03

    申请号：US14142158

    申请日：2013-12-27

    申请人： Sung-Min HWANG ,  Hansoo KIM ,  Woonkyung LEE ,  Wonseok CHO

    发明人： Sung-Min HWANG ,  Hansoo KIM ,  Woonkyung LEE ,  Wonseok CHO

    IPC分类号： H01L23/498

    CPC分类号： G11C16/0483 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A three-dimensional semiconductor device includes a substrate having a cell array region between first and second contact regions. A first stack includes a plurality of first electrodes vertically provided on the substrate, and a second stack includes a plurality of second electrodes vertically provided on the first stack. The second stack is arranged to expose end portions of the first electrodes on the first contact region and overlap end portions of the first electrodes on the second contact region.

    摘要翻译： 三维半导体器件包括在第一和第二接触区域之间具有单元阵列区域的衬底。 第一堆叠包括垂直设置在基板上的多个第一电极，第二堆叠包括垂直设置在第一堆叠上的多个第二电极。 第二堆叠被布置成暴露第一接触区域上的第一电极的端部并且在第二接触区域上重叠第一电极的端部。

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20110284943A1

    公开(公告)日：2011-11-24

    申请号：US13106481

    申请日：2011-05-12

    申请人： Sung-Min HWANG ,  Hansoo KIM ,  Wonseok CHO ,  Jaehoon JANG ,  Jae-Joo SHIM

    发明人： Sung-Min HWANG ,  Hansoo KIM ,  Wonseok CHO ,  Jaehoon JANG ,  Jae-Joo SHIM

    IPC分类号： H01L29/78

    CPC分类号： H01L27/0207 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

    摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: a plurality of conductive patterns stacked on a substrate and spaced apart from each other and a pad pattern including a flat portion extending in a first direction parallel to the substrate from one end of any one of the plurality of conductive patterns, and a landing sidewall portion extending upward from a top surface of the flat portion, wherein a width of a portion of the landing sidewall portion in a second direction parallel to the substrate and perpendicular to the first direction is less than a width of the flat portion.

    摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括：多个导电图案，其堆叠在基板上并彼此间隔开;以及焊盘图案，其包括从多个导电图案中的任一个的一端平行于基板延伸的平坦部分， 以及从所述平坦部分的顶表面向上延伸的着陆侧壁部分，其中所述着陆侧壁部分在平行于所述基板并且垂直于所述第一方向的第二方向上的一部分的宽度小于所述平坦部分的宽度 。

    3D SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SAME
    8.
    发明申请
    3D SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SAME 有权

    公开(公告)号：US20120119287A1

    公开(公告)日：2012-05-17

    申请号：US13297493

    申请日：2011-11-16

    申请人： Sang-Yong PARK ,  Jintaek PARK ,  Hansoo KIM ,  Juhyuck CHUNG ,  Wonseok CHO

    发明人： Sang-Yong PARK ,  Jintaek PARK ,  Hansoo KIM ,  Juhyuck CHUNG ,  Wonseok CHO

    IPC分类号： H01L29/78

    CPC分类号： H01L21/823475 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/7926

    摘要： A three dimensional (3D) semiconductor device includes; a vertical channel extending from a lower end proximate a substrate to an upper end and connecting a plurality of memory cells, and a cell array comprising the plurality of cells, wherein the cell array is arranged in a gate stack of layers having a stair-stepped structure disposed on the substrate. The gate stack includes a lower layer including a lower select line coupled to a lower non-memory transistor proximate the lower end, upper layers including conductive lines respectively coupled to an upper non-memory transistor proximate the upper end and connected as a single conductive piece to form an upper select line, and intermediate layers respectively including a word line and coupled to a cell transistor, wherein the intermediate layers are disposed between the lower select line and the upper select line.

    摘要翻译： 三维（3D）半导体器件包括： 垂直通道，其从靠近基板的下端延伸到上端并连接多个存储单元;以及包括所述多个单元的单元阵列，其中所述单元阵列布置在具有台阶的层的栅堆叠中 结构设置在基板上。 栅极堆叠包括下层，其包括耦合到靠近下端的下部非存储晶体管的下部选择线，上层包括分别耦合到靠近上端的上部非存储晶体管的导线，并且作为单个导电片连接 以形成上部选择线，以及分别包括字线并耦合到单元晶体管的中间层，其中中间层设置在下部选择线和上部选择线之间。

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME
    9.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME 有权
    三维半导体存储器件及其制造方法

    公开(公告)号：US20120205722A1

    公开(公告)日：2012-08-16

    申请号：US13366818

    申请日：2012-02-06

    申请人： Jaegoo LEE ,  Kil-Su JEONG ,  Hansoo KIM ,  Youngwoo PARK

    发明人： Jaegoo LEE ,  Kil-Su JEONG ,  Hansoo KIM ,  Youngwoo PARK

    IPC分类号： H01L23/52

    CPC分类号： H01L23/52 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Example embodiments relate to a three-dimensional semiconductor memory device including an electrode structure on a substrate, the electrode structure including at least one conductive pattern on a lower electrode, and a semiconductor pattern extending through the electrode structure to the substrate. A vertical insulating layer may be between the semiconductor pattern and the electrode structure, and a lower insulating layer may be between the lower electrode and the substrate. The lower insulating layer may be between a bottom surface of the vertical insulating layer and a top surface of the substrate. Example embodiments related to methods for fabricating the foregoing three-dimensional semiconductor memory device.

    摘要翻译： 示例实施例涉及一种三维半导体存储器件，其包括在衬底上的电极结构，该电极结构包括在下电极上的至少一个导电图案，以及半导体图案，其延伸穿过该电极结构到该衬底。 垂直绝缘层可以在半导体图案和电极结构之间，下绝缘层可以位于下电极和衬底之间。 下绝缘层可以在垂直绝缘层的底表面和基板的顶表面之间。 与制造上述三维半导体存储器件的方法相关的示例实施例。