公开(公告)号：US20190152020A1

公开(公告)日：2019-05-23

申请号：US15927346

申请日：2018-03-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： CHUN-KAI LAN ,  TUNG-HE CHOU ,  MING-TUNG WU ,  SHENG-CHAU CHEN ,  HSUN-CHUNG KUANG

IPC: B24B53/017 ,  B24B53/12 ,  B24B37/005 ,  B24B37/27 ,  B24B37/24 ,  H01L21/306

Abstract: An apparatus for chemical mechanical polishing includes a pad conditioner. The pad conditioner includes a first disk having a first surface and a second disk having a second surface. The first surface has a first plurality of abrasives with a first mean size and the second surface has a second plurality of abrasives with a second mean size greater than the first mean size.

公开(公告)号：US20190157170A1

公开(公告)日：2019-05-23

申请号：US15937245

申请日：2018-03-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： YU-MIN CHEN ,  CHIN-WEI LIANG ,  SHENG-CHAU CHEN ,  HSUN-CHUNG KUANG

IPC: H01L21/66 ,  G01N17/02 ,  B24B37/013 ,  H01L21/306

Abstract: A method for estimating film thickness in CMP includes the following operations. A substrate with a film formed thereon is disposed over a polishing pad with a slurry dispensed between the film and the polishing pad. A CMP operation is performed to reduce a thickness of the film. An in-situ electrochemical impedance spectroscopy (EIS) measurement is performed during the CMP operation by an EIS device to estimate the thickness of the film real-time. The CMP operation is ended when the estimated thickness of the film obtained from the fit parameters of the first equivalent electrical circuit model reaches a target thickness.

公开(公告)号：US20250008244A1

公开(公告)日：2025-01-02

申请号：US18344807

申请日：2023-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： MING-HSIEN YANG ,  CHIA-YU WEI ,  CHUN-HAO CHOU ,  KUO-CHENG LEE ,  CHUNG-LIANG CHENG ,  SHENG-CHAU CHEN

IPC: H04N25/79

Abstract: A stacked CMOS image sensor (CIS) structure is provided. The stacked CIS structure comprises a first die, a second die and a third die. The first die comprises a photodiode, a transfer gate, a selective conversion gain (SCG) switch, a reset switch, a floating node diffusion capacitor and a SCG diffusion capacitor. The second die comprises a source follower transistor and a row select switch. The third die comprises an image sensing circuit electrically connected to the third floating node.

公开(公告)号：US20200243583A1

公开(公告)日：2020-07-30

申请号：US16847331

申请日：2020-04-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： SHENG-CHAU CHEN ,  CHENG-HSIEN CHOU ,  MIN-FENG KAO

IPC: H01L27/146

Abstract: A semiconductor structure includes: a semiconductor substrate arranged over a back end of line (BEOL) metallization stack, and including a scribe line opening; a conductive pad having an upper surface that is substantially flush with an upper surface of the semiconductor substrate, the conductive pad including an upper conductive region and a lower conductive region, the upper conductive region being confined to the scribe line opening substantially from the upper surface of the semiconductor substrate to a bottom of the scribe line opening, and the lower conductive region protruding downward from the upper conductive region, through the BEOL metallization stack; a passivation layer arranged over the semiconductor substrate; and an array of pixel sensors arranged in the semiconductor substrate adjacent to the conductive pad.

公开(公告)号：US20190109185A1

公开(公告)日：2019-04-11

申请号：US16205065

申请日：2018-11-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： MING-CHE LEE ,  I-NAN CHEN ,  SHENG-CHAU CHEN ,  CHENG-HSIEN CHOU ,  CHENG-YUAN TSAI

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/31 ,  H01L27/01 ,  H01L23/00

Abstract: A semiconductor structure includes: a substrate; a first passivation layer over the substrate; a second passivation layer over the first passivation layer; and a magnetic core in the second passivation layer; wherein the magnetic core includes a first magnetic material layer and a second magnetic material layer over the first magnetic material layer, the first magnetic material layer and the second magnetic material layer are separated by a high resistance isolation layer, and the high resistance isolation layer has a resistivity greater than about 1.3 ohm-cm.

公开(公告)号：US20250089387A1

公开(公告)日：2025-03-13

申请号：US18959639

申请日：2024-11-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： SHENG-CHAU CHEN ,  CHENG-HSIEN CHOU ,  MIN-FENG KAO

IPC: H01L27/146

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes the operations as follows. A first opening is formed at a surface of a semiconductor substrate to expose a portion of an isolation region embedded in the semiconductor substrate. A buffer layer is formed over the surface of the semiconductor substrate and lining the first opening. A second opening is formed at a bottom of the first opening. A barrier layer is formed over the surface of the semiconductor substrate. A conductive pad is formed in the first and the second openings. The barrier layer includes an upper portion in contact with the buffer layer in the first opening and a lower portion lining the second opening. The lower portion of the barrier layer is free from surrounded by the buffer layer. A method for manufacturing a BSI image sensor is also provided.

公开(公告)号：US20230352516A1

公开(公告)日：2023-11-02

申请号：US18346837

申请日：2023-07-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： SHENG-CHAU CHEN ,  CHENG-HSIEN CHOU ,  MIN-FENG KAO

IPC: H01L27/146

CPC classification number: H01L27/1464 ,  H01L27/14609 ,  H01L27/14643 ,  H01L27/1463 ,  H01L27/14627 ,  H01L27/14621 ,  H01L27/14685 ,  H01L27/1462 ,  H01L27/14636

Abstract: A semiconductor structure includes: a semiconductor substrate arranged over a back end of line (BEOL) metallization stack, and including a scribe line opening; a conductive pad having an upper surface that is substantially flush with an upper surface of the semiconductor substrate, the conductive pad including an upper conductive region and a lower conductive region, the upper conductive region being confined to the scribe line opening substantially from the upper surface of the semiconductor substrate to a bottom of the scribe line opening, and the lower conductive region protruding downward from the upper conductive region, through the BEOL metallization stack; a passivation layer arranged over the semiconductor substrate; and an array of pixel sensors arranged in the semiconductor substrate adjacent to the conductive pad.

公开(公告)号：US20190259789A1

公开(公告)日：2019-08-22

申请号：US16404436

申请日：2019-05-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： SHENG-CHAU CHEN ,  CHENG-HSIEN CHOU ,  MIN-FENG KAO

IPC: H01L27/146

Abstract: A semiconductor structure includes: a semiconductor substrate arranged over a back end of line (BEOL) metallization stack, and including a scribe line opening; a conductive pad having an upper surface that is substantially flush with an upper surface of the semiconductor substrate, the conductive pad including an upper conductive region and a lower conductive region, the upper conductive region being confined to the scribe line opening substantially from the upper surface of the semiconductor substrate to a bottom of the scribe line opening, and the lower conductive region protruding downward from the upper conductive region, through the BEOL metallization stack; a passivation layer arranged over the semiconductor substrate; and an array of pixel sensors arranged in the semiconductor substrate adjacent to the conductive pad.

公开(公告)号：US20170194273A1

公开(公告)日：2017-07-06

申请号：US15156764

申请日：2016-05-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： SHENG-CHAU CHEN ,  SHIH-PEI CHOU ,  MING-JHE LEE ,  KUO-MING WU ,  CHENG-HSIEN CHOU ,  CHENG-YUAN TSAI ,  YEUR-LUEN TU

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L23/481 ,  H01L24/02 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/05019 ,  H01L2224/05082 ,  H01L2224/05088 ,  H01L2224/05091 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/0603 ,  H01L2224/06182 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/9222 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/80 ,  H01L2224/11 ,  H01L2224/0231 ,  H01L2224/03 ,  H01L21/304 ,  H01L21/76898 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/00012

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductive substrate and an interconnect structure over the semiconductive substrate. The semiconductor structure also comprises a bond pad in the semiconductive substrate and coupled to the metal layer. The bond pad comprises two conductive layers.

公开(公告)号：US20210242303A1

公开(公告)日：2021-08-05

申请号：US17238041

申请日：2021-04-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： MING-CHE LEE ,  SHENG-CHAU CHEN ,  I-NAN CHEN ,  CHENG-HSIEN CHOU ,  CHENG-YUAN TSAI

IPC: H01L49/02 ,  H01L23/31 ,  H01L27/01 ,  H01L23/00 ,  H01L23/522

Abstract: A semiconductor structure includes: a substrate; a first passivation layer over the substrate; a second passivation layer over the first passivation layer; and a magnetic core in the second passivation layer, wherein the magnetic core includes a first magnetic material layer and a second magnetic material layer over the first magnetic material layer, the first magnetic material layer and the second magnetic material layer are separated by a high resistance isolation layer, and the high resistance isolation layer has a resistivity greater than about 1.3 ohm-cm.