公开(公告)号：US10256323B2

公开(公告)日：2019-04-09

申请号：US15456269

申请日：2017-03-10

申请人： Toyoda Gosei Co., Ltd.

发明人： Nariaki Tanaka ,  Tohru Oka

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/285 ,  H01L21/324 ,  H01L29/10 ,  H01L29/20 ,  H01L29/423 ,  H01L29/78 ,  H01L21/265

摘要： A technique of improving the breakdown voltage of a semiconductor device is provided. There is provided a method of manufacturing a semiconductor device comprising a process of forming a p-type semiconductor layer that contains a p-type impurity and has a dislocation density of not higher than 1.0×107 cm−2, on an n-type semiconductor layer that contains an n-type impurity and has a dislocation density of not higher than 1.0×107 cm−2; an n-type semiconductor region forming process of forming an n-type semiconductor region in at least part of the p-type semiconductor layer by ion-implanting an n-type impurity into the p-type semiconductor layer and performing heat treatment to activate the ion-implanted n-type impurity; and a process of forming a trench that is recessed to pass through the p-type semiconductor layer and reach the n-type semiconductor layer. In the n-type semiconductor region forming process, a p-type impurity diffusion region in which the p-type impurity contained in the p-type semiconductor layer is diffused is formed in at least part of the n-type semiconductor layer that is located below the n-type semiconductor region.

公开(公告)号：US20160254392A1

公开(公告)日：2016-09-01

申请号：US15046530

申请日：2016-02-18

申请人： TOYODA GOSEI CO., LTD.

发明人： Kazuya Hasegawa ,  Tohru Oka ,  Nariaki Tanaka

IPC分类号： H01L29/872 ,  H01L29/47 ,  H01L21/311 ,  H01L29/66 ,  H01L21/285 ,  H01L29/06 ,  H01L29/45

CPC分类号： H01L29/872 ,  H01L21/28537 ,  H01L21/28581 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/0657 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/407 ,  H01L29/456 ,  H01L29/47 ,  H01L29/6606 ,  H01L29/66143 ,  H01L29/66212 ,  H01L29/66969

摘要： A semiconductor device comprises a semiconductor layer including a mesa structure and a peripheral surface extending around the mesa structure, the mesa structure having a plateau shape with an upper surface and a side surface; a Schottky electrode forming a Schottky junction with the upper surface; an insulating film extending from the peripheral surface, across the side surface, and onto the Schottky electrode, the insulating film having an opening formed on the Schottky electrode; and a wiring electrode electrically connected to the Schottky electrode inside the opening, the wiring electrode extending from inside of the opening, across a portion of the insulating film formed on the side surface, and onto another portion of the insulating film formed on the peripheral surface.

摘要翻译： 半导体器件包括包括台面结构的半导体层和围绕台面结构延伸的周边表面，台面结构具有上表面和侧表面的平台形状; 肖特基电极与上表面形成肖特基结; 绝缘膜，其从外周面延伸穿过所述侧面，并且在所述肖特基电极上，所述绝缘膜具有形成在所述肖特基电极上的开口; 以及配线电极，与所述开口内的所述肖特基电极电连接，所述布线电极从所述开口的内部延伸穿过形成在所述侧面的所述绝缘膜的一部分，以及形成在所述周面的所述绝缘膜的另一部分 。

公开(公告)号：US20140167148A1

公开(公告)日：2014-06-19

申请号：US14104980

申请日：2013-12-12

申请人： TOYODA GOSEI CO., LTD.

发明人： Toru Oka ,  Nariaki Tanaka

IPC分类号： H01L29/417 ,  H01L29/78

CPC分类号： H01L29/41741 ,  H01L21/0485 ,  H01L21/28575 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/45 ,  H01L29/452 ,  H01L29/66068 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813

摘要： A semiconductor device includes: a p-type semiconductor layer; an n-type semiconductor layer; a first electrode layer; a second electrode layer; and a control electrode layer. The first and second electrode layers are electrically connected such as to each operate at an identical potential. The first electrode layer is connected with a part of a surface of the second electrode layer which is opposite to a surface of the second electrode layer that is in contact with the p-type semiconductor layer. The second electrode layer is connected with a connection line which is a part of a peripheral line of a joint interface between the p-type semiconductor layer and the n-type semiconductor layer on an interface side between the second electrode layer and the p-type semiconductor layer, and is formed to be extended to a position on a control electrode layer side of the connection line.

摘要翻译： 一种半导体器件包括：p型半导体层; n型半导体层; 第一电极层; 第二电极层; 和控制电极层。 第一和第二电极层电连接，以便各自以相同的电位工作。 第一电极层与第二电极层的与p型半导体层接触的与第二电极层的表面相对的一部分表面连接。 第二电极层与作为p型半导体层和n型半导体层之间的接合界面的外围线的一部分的连接线连接在第二电极层和p型之间的界面侧 半导体层，并且形成为延伸到连接线的控制电极层侧的位置。

公开(公告)号：US10832911B2

公开(公告)日：2020-11-10

申请号：US16555960

申请日：2019-08-29

申请人： TOYODA GOSEI CO., LTD.

发明人： Nariaki Tanaka ,  Toru Oka ,  Yukihisa Ueno ,  Kota Yasunishi

IPC分类号： H01L21/04 ,  H01L29/87 ,  H01L21/02 ,  H01L29/872 ,  H01L29/47 ,  H01L21/225 ,  H01L29/20

摘要： An n-type GaN layer, a p-type diffusion region formed by ion implantation and annealing in a part of the n-type layer, and a Schottky electrode are formed on the n-type layer. A region without the p-type region is defined as region A, and a region with the p-type region is defined as region B. In region A, an average density of each electron trap level of the n-type layer in a region having a depth of 0.8 μm to 1.6 μm on the n-type layer side is set so as to satisfy the predetermined conditions. In region B, an average density of each carrier trap level of the n-type layer in a region having a depth of 0.8 μm to 1.6 μm on the n-type layer side from a boundary between the n-type layer and the p-type diffusion region is set so as to satisfy the predetermined conditions.

公开(公告)号：US09985127B2

公开(公告)日：2018-05-29

申请号：US15464112

申请日：2017-03-20

申请人： TOYODA GOSEI CO., LTD.

发明人： Yukihisa Ueno ,  Nariaki Tanaka

IPC分类号： H01L29/78 ,  H01L29/20 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L21/265 ,  H01L29/40 ,  H01L29/06

CPC分类号： H01L29/7813 ,  H01L21/2654 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66734 ,  H01L29/7811

摘要： To improve the breakdown voltage of a semiconductor device. In a terminal region of the semiconductor device, a mesa groove, a recess groove, an electric field relaxation region, and a gradient distributed low concentration p-type layer region are formed. A recess groove is fromed between a device region and the mesa groove so as to surround the device region. A region where a p-type layer is thinned by the recess groove is the electric field relaxation region. The gradient distributed low concentration p-type layer region is formed on the surface of the electric field relaxation region. The average carrier concentration of the entire gradient distributed low concentration p-type layer region is lower than the carrier concentration of the p-type layer. By forming the gradient distributed low concentration p-type layer region, the electric field relaxation region is quickly completely depleted when a reverse voltage is applied, thereby improving the breakdown voltage.

公开(公告)号：US10153356B2

公开(公告)日：2018-12-11

申请号：US15460069

申请日：2017-03-15

申请人： TOYODA GOSEI CO., LTD.

发明人： Tohru Oka ,  Nariaki Tanaka

IPC分类号： H01L29/66 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L29/10 ,  H01L29/20 ,  H01L29/207 ,  H01L29/78 ,  H01L21/324

摘要： A technique of suppressing the potential crowding in the vicinity of the outer periphery of a bottom face of a trench without ion implantation of a p-type impurity is provided. A method of manufacturing a semiconductor device having a trench gate structure comprises an n-type semiconductor region forming process. In the n-type semiconductor region forming process, a p-type impurity diffusion region in which a p-type impurity contained in a p-type semiconductor layer is diffused is formed in at least part of an n-type semiconductor layer that is located below an n-type semiconductor region.

公开(公告)号：US10153352B2

公开(公告)日：2018-12-11

申请号：US15449745

申请日：2017-03-03

申请人： TOYODA GOSEI CO., LTD.

发明人： Nariaki Tanaka ,  Tohru Oka

IPC分类号： H01L29/15 ,  H01L29/45 ,  H01L21/02 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/324 ,  H01L29/20 ,  H01L29/423 ,  H01L29/778

摘要： A technique of reducing the complication in manufacture is provided. There is provided a semiconductor device comprising an n-type semiconductor region made of a nitride semiconductor containing gallium; a p-type semiconductor region arranged to be adjacent to and in contact with the n-type semiconductor region and made of the nitride semiconductor; a first electrode arranged to be in ohmic contact with the n-type semiconductor region; and a second electrode arranged to be in ohmic contact with the p-type semiconductor region. The first electrode and the second electrode are mainly made of one identical metal. The identical metal is at least one metal selected from the group consisting of palladium, nickel and platinum. A concentration of a p-type impurity in the n-type semiconductor region is approximately equal to a concentration of the p-type impurity in the p-type semiconductor region. A difference between a concentration of an n-type impurity and the concentration of the p-type impurity in the n-type semiconductor region is not less than 1.0×1019 cm−3.

公开(公告)号：US20170278950A1

公开(公告)日：2017-09-28

申请号：US15456269

申请日：2017-03-10

申请人： Toyoda Gosei Co., Ltd.

发明人： Nariaki Tanaka ,  Tohru Oka

IPC分类号： H01L29/66 ,  H01L29/10 ,  H01L21/285 ,  H01L29/423 ,  H01L21/02 ,  H01L21/324 ,  H01L29/20 ,  H01L29/78

CPC分类号： H01L29/66666 ,  H01L21/02389 ,  H01L21/0254 ,  H01L21/26553 ,  H01L21/28587 ,  H01L21/3245 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66522 ,  H01L29/7813 ,  H01L29/7827

摘要： A technique of improving the breakdown voltage of a semiconductor device is provided. There is provided a method of manufacturing a semiconductor device comprising a process of forming a p-type semiconductor layer that contains a p-type impurity and has a dislocation density of not higher than 1.0×107 cm−2, on an n-type semiconductor layer that contains an n-type impurity and has a dislocation density of not higher than 1.0×107 cm−2; an n-type semiconductor region forming process of forming an n-type semiconductor region in at least part of the p-type semiconductor layer by ion-implanting an n-type impurity into the p-type semiconductor layer and performing heat treatment to activate the ion-implanted n-type impurity; and a process of forming a trench that is recessed to pass through the p-type semiconductor layer and reach the n-type semiconductor layer. In the n-type semiconductor region forming process, a p-type impurity diffusion region in which the p-type impurity contained in the p-type semiconductor layer is diffused is formed in at least part of the n-type semiconductor layer that is located below the n-type semiconductor region.

公开(公告)号：US09685348B2

公开(公告)日：2017-06-20

申请号：US15055357

申请日：2016-02-26

申请人： TOYODA GOSEI CO., LTD.

发明人： Tsutomu Ina ,  Tohru Oka ,  Nariaki Tanaka

IPC分类号： H01L21/3213 ,  H01L29/45

CPC分类号： H01L21/32135 ,  H01L21/28575 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/452 ,  H01L29/7786

摘要： An object is to avoid an increase in contact resistance of an ohmic electrode by etching in a semiconductor device. There is provided a method of manufacturing a semiconductor device. The method of manufacturing comprises forming a semiconductor layer; forming an ohmic electrode by stacking a plurality of metal layers, on the semiconductor layer; forming another metal layer that is mainly made of another metal different from a material of an outermost layer among the plurality of metal layers, on the ohmic electrode; removing the another metal layer from top of the ohmic electrode by etching; and processing the ohmic electrode by heat treatment, subsequent to the etching.

公开(公告)号：US09443950B2

公开(公告)日：2016-09-13

申请号：US14104998

申请日：2013-12-12

申请人： TOYODA GOSEI CO., LTD.

发明人： Toru Oka ,  Nariaki Tanaka

IPC分类号： H01L29/06 ,  H01L29/45 ,  H01L21/04 ,  H01L21/285 ,  H01L29/66 ,  H01L29/78 ,  H01L29/20 ,  H01L29/16 ,  H01L29/40 ,  H01L29/417 ,  H01L29/10

CPC分类号： H01L29/45 ,  H01L21/0485 ,  H01L21/28587 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/452 ,  H01L29/66068 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813

摘要： A semiconductor device includes: a p-type semiconductor layer; an n-type semiconductor layer connected with the p-type semiconductor layer; a first electrode layer formed on the n-type semiconductor layer; and a second electrode layer formed on the p-type semiconductor layer. The first electrode layer and the second electrode layer are electrically connected such as to each operate at an identical potential. The second electrode layer is connected with at least a part of a surface of the first electrode layer which is opposite to a surface of the first electrode layer that is in contact with the n-type semiconductor layer.

摘要翻译： 半导体器件包括：p型半导体层; 与p型半导体层连接的n型半导体层; 形成在所述n型半导体层上的第一电极层; 以及形成在p型半导体层上的第二电极层。 第一电极层和第二电极层电连接，以使其各自以相同的电位工作。 第二电极层与第一电极层的与n型半导体层接触的与第一电极层的表面相对的表面的至少一部分连接。