公开(公告)号：US20250149488A1

公开(公告)日：2025-05-08

申请号：US18585599

申请日：2024-02-23

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Wei-Yu Chen ,  Chao-Wei Chiu ,  Hsin Liang Chen ,  Hao-Jan Shih ,  Hao-Jan Pei ,  Hsiu-Jen Lin

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: In an embodiment, a method includes forming a device region along a first substrate; forming an interconnect structure over the device region and the first substrate; forming a metal pillar over the interconnect structure, forming the metal pillar comprising: forming a base layer over the interconnect structure; forming an intermediate layer over the base layer; and forming a capping layer over the intermediate layer; forming a solder region over the capping layer; and performing an etch process to recess sidewalls of the base layer and the capping layer from sidewalls of the intermediate layer and the solder region.

公开(公告)号：US11049832B2

公开(公告)日：2021-06-29

申请号：US16876371

申请日：2020-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Jan Pei ,  Chih-Chiang Tsao ,  Wei-Yu Chen ,  Hsiu-Jen Lin ,  Ming-Da Cheng ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L21/00 ,  H01L25/10 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31 ,  H01L21/683 ,  H01L25/11

Abstract: A method for forming a package structure is provided. The method includes forming a protective layer to surround a semiconductor die and forming a conductive structure over the protective layer. The method also includes disposing a polymer-containing material over the protective layer to partially surround the conductive structure. The method further includes curing the polymer-containing material to form a warpage-control element.

公开(公告)号：US12040309B2

公开(公告)日：2024-07-16

申请号：US17815713

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Chia-Shen Cheng ,  Hao-Jan Pei ,  Philip Yu-Shuan Chung ,  Kuei-Wei Huang ,  Yu-Peng Tsai ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh ,  Chen-Hua Yu ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/49822 ,  H01L24/17 ,  H01L2224/175 ,  H01L2224/81224 ,  H01L2924/3511

Abstract: A method includes performing a first laser shot on a first portion of a top surface of a first package component. The first package component is over a second package component, and a first solder region between the first package component and the second package component is reflowed by the first laser shot. After the first laser shot, a second laser shot is performed on a second portion of the top surface of the first package component. A second solder region between the first package component and the second package component is reflowed by the second laser shot.

公开(公告)号：US20240153842A1

公开(公告)日：2024-05-09

申请号：US18404504

申请日：2024-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Jan Pei ,  Wei-Yu Chen ,  Chia-Shen Cheng ,  Chih-Chiang Tsao ,  Cheng-Ting Chen ,  Chia-Lun Chang ,  Chih-Wei Lin ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC: H01L23/373 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/50 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L23/3736 ,  H01L21/486 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/83 ,  H01L25/105 ,  H01L23/49816 ,  H01L2924/15311

Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.

公开(公告)号：US11901258B2

公开(公告)日：2024-02-13

申请号：US17227790

申请日：2021-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Jan Pei ,  Wei-Yu Chen ,  Chia-Shen Cheng ,  Chih-Chiang Tsao ,  Cheng-Ting Chen ,  Chia-Lun Chang ,  Chih-Wei Lin ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC: H01L23/373 ,  H01L23/50 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L25/10 ,  H01L23/367 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L23/3736 ,  H01L21/486 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/83 ,  H01L25/105 ,  H01L23/49816 ,  H01L2224/18 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/29099

Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.

公开(公告)号：US20230386862A1

公开(公告)日：2023-11-30

申请号：US18447409

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Hao-Jan Pei ,  Hsuan-Ting Kuo ,  Chih-Chiang Tsao ,  Jen-Jui Yu ,  Philip Yu-Shuan Chung ,  Chia-Lun Chang ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh

IPC: H01L21/50 ,  H01L21/48 ,  H01L23/00 ,  B23K1/00 ,  H01L21/60

CPC classification number: H01L21/50 ,  H01L21/4853 ,  H01L24/10 ,  B23K1/0016 ,  H01L2021/60225 ,  H01L2021/60135

Abstract: A method includes forming regions of solder paste on a redistribution structure, wherein the solder paste has a first melting temperature; forming solder bumps on an interconnect structure, wherein the solder bumps have a second melting temperature that is greater than the first melting temperature; placing the solder bumps on the regions of solder paste; performing a first reflow process at a first reflow temperature for a first duration of time, wherein the first reflow temperature is less than the second melting temperature; and after performing the first reflow process, performing a second reflow process at a second reflow temperature for a second duration of time, wherein the second reflow temperature is greater than the second melting temperature.

公开(公告)号：US11462507B2

公开(公告)日：2022-10-04

申请号：US17034917

申请日：2020-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Chia-Shen Cheng ,  Hao-Jan Pei ,  Philip Yu-Shuan Chung ,  Kuei-Wei Huang ,  Yu-Peng Tsai ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh ,  Chen-Hua Yu ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56

Abstract: A method includes performing a first laser shot on a first portion of a top surface of a first package component. The first package component is over a second package component, and a first solder region between the first package component and the second package component is reflowed by the first laser shot. After the first laser shot, a second laser shot is performed on a second portion of the top surface of the first package component. A second solder region between the first package component and the second package component is reflowed by the second laser shot.

公开(公告)号：US20220216071A1

公开(公告)日：2022-07-07

申请号：US17141835

申请日：2021-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Hao-Jan Pei ,  Hsuan-Ting Kuo ,  Chih-Chiang Tsao ,  Jen-Jui Yu ,  Philip Yu-Shuan Chung ,  Chia-Lun Chang ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh

IPC: H01L21/50 ,  H01L23/00 ,  H01L21/48

Abstract: A method includes forming regions of solder paste on a redistribution structure, wherein the solder paste has a first melting temperature; forming solder bumps on an interconnect structure, wherein the solder bumps have a second melting temperature that is greater than the first melting temperature; placing the solder bumps on the regions of solder paste; performing a first reflow process at a first reflow temperature for a first duration of time, wherein the first reflow temperature is less than the second melting temperature; and after performing the first reflow process, performing a second reflow process at a second reflow temperature for a second duration of time, wherein the second reflow temperature is greater than the second melting temperature.

公开(公告)号：US11211341B2

公开(公告)日：2021-12-28

申请号：US16719984

申请日：2019-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Jan Pei ,  Ching-Hua Hsieh ,  Hsiu-Jen Lin ,  Wei-Yu Chen ,  Chia-Shen Cheng ,  Chih-Chiang Tsao ,  Jen-Jui Yu ,  Cheng-Shiuan Wong

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498

Abstract: Provided is a package structure, including a die, a plurality of through vias, an encapsulant, a plurality of first connectors, a warpage control material and a protection material. The plurality of through vias are disposed around the die. The encapsulant laterally encapsulate the die and the plurality of through vias. The plurality of first connectors are electrically connected to the plurality of through vias. The warpage control material is disposed over a first surface of the die. The protection material is disposed over the encapsulant, around the plurality of first connectors and the warpage control material.

公开(公告)号：US10658323B2

公开(公告)日：2020-05-19

申请号：US16398119

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Hao-Jan Pei ,  Chih-Chiang Tsao ,  Wei-Yu Chen ,  Hsiu-Jen Lin ,  Ming-Da Cheng ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC: H01L21/00 ,  H01L23/00 ,  H01L25/11 ,  H01L25/10 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31 ,  H01L21/683

Abstract: A package structure is provided. The package structure includes a semiconductor die and a protective layer surrounding the semiconductor die. The package structure also includes a conductive structure and a warpage-control element over a same side of the protective layer. A bottom surface of the warpage-control element is higher than a bottom surface of the conductive structure. The bottom surface of the warpage-control element is lower than a top surface of the conductive bump.