公开(公告)号：US20230387101A1

公开(公告)日：2023-11-30

申请号：US17828310

申请日：2022-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Haw Tsao ,  Chien-Li Kuo ,  Kuo-Chio Liu

IPC: H01L25/00 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L21/60 ,  H01L2021/6006

Abstract: In an embodiment, a method of forming an integrated circuit package includes: attaching a first carrier to a package component, the package component comprising: an interposer; a first semiconductor die attached to a first side of the interposer; a second semiconductor die attached to the first side of the interposer; an encapsulant encapsulating the first semiconductor die and the second semiconductor die; and conductive connectors attached to a second side of the interposer; attaching a second carrier to a package substrate, the package substrate comprising bond pads; bonding the conductive connectors of the package component to the bond pads of the package substrate by reflowing the conductive connectors while the first carrier is attached to the package component and while the second carrier is attached to the package substrate; removing the first carrier; and removing the second carrier.

公开(公告)号：US11257797B2

公开(公告)日：2022-02-22

申请号：US16689101

申请日：2019-11-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Dong-Han Shen ,  Chen-Shien Chen ,  Kuo-Chio Liu ,  Hsi-Kuei Cheng ,  Yi-Jen Lai

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L25/18 ,  H01L23/538 ,  H01L25/065

Abstract: A package on package structure includes a first package, a plurality of conductive bumps, a second package and an underfill. The conductive bumps are disposed on a second surface of the first package and electrically connected to the first package. The second package is disposed on the second surface of the first package through the conductive bumps, and includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. A shortest distance from an upper surface of the encapsulating material to an upper surface of the semiconductor device is greater than or substantially equal to twice a thickness of the semiconductor device. The underfill is filled between the first package and the second package.

公开(公告)号：US10811377B2

公开(公告)日：2020-10-20

申请号：US16194927

申请日：2018-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hung Chen ,  Yu-Nu Hsu ,  Chun-Chen Liu ,  Heng-Chi Huang ,  Chien-Chen Li ,  Shih-Yen Chen ,  Cheng-Nan Hsieh ,  Kuo-Chio Liu ,  Chen-Shien Chen ,  Chin-Yu Ku ,  Te-Hsun Pang ,  Yuan-Feng Wu ,  Sen-Chi Chiang

IPC: H01L23/20 ,  H01L23/498 ,  H01L23/00

Abstract: A package structure is provided. The package structure includes a first bump structure formed over a substrate, a solder joint formed over the first bump structure and a second bump structure formed over the solder joint. The first bump structure includes a first pillar layer formed over the substrate and a first barrier layer formed over the first pillar layer. The first barrier layer has a first protruding portion which extends away from a sidewall surface of the first pillar layer, and a distance between the sidewall surface of the first pillar layer and a sidewall surface of the first barrier layer is in a range from about 0.5 μm to about 3 μm. The second bump structure includes a second barrier layer formed over the solder joint and a second pillar layer formed over the second barrier layer, wherein the second barrier layer has a second protruding portion which extends away from a sidewall surface of the second pillar layer.

公开(公告)号：US20240071950A1

公开(公告)日：2024-02-29

申请号：US17898075

申请日：2022-08-29

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Wen-Yi Lin ,  Kuang-Chun Lee ,  Chien-Chen Li ,  Chien-Li Kuo ,  Kuo-Chio Liu

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L21/4817 ,  H01L21/563 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16221 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/37001

Abstract: Integrated circuit packages and methods of forming the same are discussed. In an embodiment, a device includes: a package substrate; a semiconductor device attached to the package substrate; an underfill between the semiconductor device and the package substrate; and a package stiffener attached to the package substrate, the package stiffener includes: a main body extending around the semiconductor device and the underfill in a top-down view, the main body having a first coefficient of thermal expansion; and pillars in the main body, each of the pillars extending from a top surface of the main body to a bottom surface of the main body, each of the pillars physically contacting the main body, the pillars having a second coefficient of thermal expansion, the second coefficient of thermal expansion being less than the first coefficient of thermal expansion.

公开(公告)号：US11594484B2

公开(公告)日：2023-02-28

申请号：US16915312

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mirng-Ji Lii ,  Chung-Shi Liu ,  Chin-Yu Ku ,  Hung-Jui Kuo ,  Alexander Kalnitsky ,  Ming-Che Ho ,  Yi-Wen Wu ,  Ching-Hui Chen ,  Kuo-Chio Liu

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A method includes forming a first dielectric layer over a conductive pad, forming a second dielectric layer over the first dielectric layer, and etching the second dielectric layer to form a first opening, with a top surface of the first dielectric layer exposed to the first opening. A template layer is formed to fill the first opening. A second opening is then formed in the template layer and the first dielectric layer, with a top surface of the conductive pad exposed to the second opening. A conductive pillar is formed in the second opening.

公开(公告)号：US20200328153A1

公开(公告)日：2020-10-15

申请号：US16915312

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mirng-Ji Lii ,  Chung-Shi Liu ,  Chin-Yu Ku ,  Hung-Jui Kuo ,  Alexander Kalnitsky ,  Ming-Che Ho ,  Yi-Wen Wu ,  Ching-Hui Chen ,  Kuo-Chio Liu

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/768 ,  H01L23/528

Abstract: A method includes forming a first dielectric layer over a conductive pad, forming a second dielectric layer over the first dielectric layer, and etching the second dielectric layer to form a first opening, with a top surface of the first dielectric layer exposed to the first opening. A template layer is formed to fill the first opening. A second opening is then formed in the template layer and the first dielectric layer, with a top surface of the conductive pad exposed to the second opening. A conductive pillar is formed in the second opening.

公开(公告)号：US20200091122A1

公开(公告)日：2020-03-19

申请号：US16689101

申请日：2019-11-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Dong-Han Shen ,  Chen-Shien Chen ,  Kuo-Chio Liu ,  Hsi-Kuei Cheng ,  Yi-Jen Lai

IPC: H01L25/10 ,  H01L23/538 ,  H01L25/18 ,  H01L23/31 ,  H01L23/00

Abstract: A package on package structure includes a first package, a plurality of conductive bumps, a second package and an underfill. The conductive bumps are disposed on a second surface of the first package and electrically connected to the first package. The second package is disposed on the second surface of the first package through the conductive bumps, and includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. A shortest distance from an upper surface of the encapsulating material to an upper surface of the semiconductor device is greater than or substantially equal to twice a thickness of the semiconductor device. The underfill is filled between the first package and the second package.

公开(公告)号：US10014218B1

公开(公告)日：2018-07-03

申请号：US15492525

申请日：2017-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Fu Shih ,  Cheng-Lin Huang ,  Chien-Chen Li ,  Che-Jung Chu ,  Wen-Ming Chen ,  Kuo-Chio Liu

IPC: H01L23/48 ,  H01L21/78 ,  H01L23/00 ,  H01L23/544 ,  H01L21/56 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L2223/5446 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/11011 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13011 ,  H01L2224/13013 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/16146 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/3003 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L21/304

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor structure. The semiconductor structure has a central portion and a peripheral portion surrounding the central portion. The method includes forming first conductive bumps and dummy conductive bumps over a surface of the semiconductor structure. The first conductive bumps are over the central portion and electrically connected to the semiconductor structure. The dummy conductive bumps are over the peripheral portion and electrically insulated from the semiconductor structure. The first conductive bumps each have a first thickness and a first width. The dummy conductive bumps each have a second thickness and a second width. The second thickness is less than the first thickness. The second width is greater than the first width.

公开(公告)号：US11923353B2

公开(公告)日：2024-03-05

申请号：US17874492

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Jen Lai ,  Chung-Yi Lin ,  Hsi-Kuei Cheng ,  Chen-Shien Chen ,  Kuo-Chio Liu

IPC: H01L21/683 ,  H01L21/56 ,  H01L23/00 ,  H01L23/60 ,  H01L25/00 ,  H01L25/10 ,  H01L23/31 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/60 ,  H01L24/02 ,  H01L24/96 ,  H01L25/105 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/02311 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/06182 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/16146 ,  H01L2224/18 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00

Abstract: A method includes forming a release film over a carrier, forming a polymer buffer layer over the release film, forming a metal post on the polymer buffer layer, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, and decomposing a first portion of the release film. A second portion of the release film remains after the decomposing. An opening is formed in the polymer buffer layer to expose the metal post.

公开(公告)号：US11004728B2

公开(公告)日：2021-05-11

申请号：US16741078

申请日：2020-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Sheng Tang ,  Fu-Chen Chang ,  Cheng-Lin Huang ,  Wen-Ming Chen ,  Chun-Yen Lo ,  Kuo-Chio Liu

IPC: H01L23/544 ,  H01L23/28 ,  H01L21/78 ,  H01L23/495 ,  H01L23/522 ,  H01L21/304 ,  H01L21/768 ,  H01L21/683 ,  H01L21/67 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/10 ,  H01L23/58 ,  H01L25/065 ,  H01L25/00

Abstract: A method for sawing a semiconductor wafer is provided. The method includes sawing a semiconductor wafer to form a first opening. In addition, the semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape by a die attach film (DAF), and the first opening is formed in an upper portion of the substrate. The method further includes sawing through the substrate and the DAF of the semiconductor wafer from the first opening to form a middle opening under the first opening and a second opening under the middle opening, so that the semiconductor wafer is divided into two dies. In addition, a slope of a sidewall of the middle opening is different from slopes of sidewalls of the first opening and the second opening.