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1.发明公开公开(公告)号：US20230387281A1
公开(公告)日：2023-11-30
申请号：US18364679
申请日：2023-08-03
发明人： Man-Ho Kwan , Fu-Wei Yao , Chun Lin Tsai , Jiun-Lei Jerry Yu , Ting-Fu Chang
IPC分类号： H01L29/778 , H01L29/10 , H01L29/20 , H01L29/66
CPC分类号： H01L29/7783 , H01L29/1041 , H01L29/2003 , H01L29/66462
摘要： Various embodiments of the present disclosure are directed towards an integrated chip a first undoped layer overlies a substrate. A first barrier layer overlies the first undoped layer and has a first thickness. A first doped layer overlies the first barrier layer and is disposed laterally within an n-channel device region of the substrate. A second barrier layer overlies the first barrier layer and is disposed within a p-channel device region that is laterally adjacent to the n-channel device region. The second barrier layer has a second thickness that is greater than the first thickness. A second undoped layer overlies the second barrier layer. A second doped layer overlies the second undoped layer. The second undoped layer and the second doped layer are disposed within the p-channel device region.
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公开(公告)号：US10964804B2
公开(公告)日：2021-03-30
申请号：US16390543
申请日：2019-04-22
IPC分类号： H01L29/778 , H01L29/20 , H01L21/324 , H01L29/66 , H01L29/201 , H01L29/51
摘要： A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over a top surface of the active layer; and a source/drain electrode over the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to a bottom surface of the active layer, and the first layer possesses a higher aluminum (Al) atom concentration compared to the second layer. An HEMT structure and an associated method are also disclosed.
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公开(公告)号：US10937900B2
公开(公告)日：2021-03-02
申请号：US15136309
申请日：2016-04-22
发明人： Po-Chun Liu , Chi-Ming Chen , Yao-Chung Chang , Jiun-Lei Jerry Yu , Chen-Hao Chiang , Chung-Yi Yu
IPC分类号： H01L29/20 , H01L29/66 , H01L29/778 , H01L29/49
摘要： The present disclosure provides a semiconductor structure, including a substrate, a first III-V layer over the substrate, having a first band gap, and a second III-V layer over the first III-V layer, having a second band gap. The second III-V layer includes a first surface in contact with the first III-V layer and a second surface opposite to the first surface. The second band gap at the second surface is greater than the second band gap at the first surface. The present disclosure also provides a manufacturing method of the aforesaid semiconductor structure.
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公开(公告)号：US10741665B2
公开(公告)日：2020-08-11
申请号：US16101065
申请日：2018-08-10
发明人： Chun-Wei Hsu , Jiun-Lei Jerry Yu , Fu-Wei Yao , Chen-Ju Yu , Fu-Chih Yang , Chun Lin Tsai
IPC分类号： H01L29/66 , H01L29/20 , H01L29/417 , H01L29/43 , H01L29/778 , H01L29/10 , H01L29/267 , H01L21/02
摘要： A high electron mobility transistor (HEMT) includes a first III-V compound layer and a second III-V compound layer disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A capping layer is disposed on the second III-V compound layer.
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公开(公告)号：US09871030B2
公开(公告)日：2018-01-16
申请号：US15357308
申请日：2016-11-21
发明人： King-Yuen Wong , Chun-Wei Hsu , Chen-Ju Yu , Fu-Wei Yao , Jiun-Lei Jerry Yu , Fu-Chih Yang , Po-Chih Chen
IPC分类号： H01L27/02 , H01L29/66 , H01L29/778 , H01L29/10 , H01L29/20 , H01L21/8252 , H01L27/06 , H01L21/02 , H01L21/265 , H01L21/306 , H01L21/768 , H01L21/8258 , H01L23/522 , H01L29/205 , H01L29/861
CPC分类号： H01L27/0255 , H01L21/02381 , H01L21/0254 , H01L21/26513 , H01L21/26546 , H01L21/30612 , H01L21/76877 , H01L21/76898 , H01L21/8252 , H01L21/8258 , H01L23/5226 , H01L27/0605 , H01L29/1075 , H01L29/2003 , H01L29/205 , H01L29/6609 , H01L29/66462 , H01L29/7787 , H01L29/861
摘要： A silicon substrate having a III-V compound layer disposed thereon is provided. A diode is formed in the silicon substrate through an ion implantation process. The diode is formed proximate to an interface between the silicon substrate and the III-V compound layer. An opening is etched through the III-V compound layer to expose the diode. The opening is filled with a conductive material. Thereby, a via is formed that is coupled to the diode. A High Electron Mobility Transistor (HEMT) device is formed at least partially in the III-V compound layer.
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公开(公告)号：US09224829B2
公开(公告)日：2015-12-29
申请号：US14267954
申请日：2014-05-02
发明人： King-Yuen Wong , Chen-Ju Yu , Fu-Wei Yao , Jiun-Lei Jerry Yu , Fu-Chih Yang , Po-Chih Chen , Chun-Wei Hsu
IPC分类号： H01L21/338 , H01L21/28 , H01L29/66 , H01L21/02 , H01L27/146 , H01L29/423 , H01L29/778 , H01L29/10 , H01L29/16 , H01L29/20
CPC分类号： H01L29/66462 , H01L21/0254 , H01L27/14689 , H01L29/1033 , H01L29/1608 , H01L29/2003 , H01L29/42364 , H01L29/7787
摘要： A method of forming a semiconductor structure, the method includes epitaxially growing a second III-V compound layer on a first III-V compound layer. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. The method further includes forming a source feature and a drain feature on the second III-V compound layer, forming a third III-V compound layer on the second III-V compound layer, depositing a gate dielectric layer on a portion of the second III-V compound layer and a top surface of the third III-V compound layer, treating the gate dielectric layer on the portion of the second III-V compound layer with fluorine and forming a gate electrode on the treated gate dielectric layer between the source feature and the drain feature.
摘要翻译： 一种形成半导体结构的方法，所述方法包括在第一III-V化合物层上外延生长第二III-V化合物层。 载体通道位于第一III-V化合物层和第二III-V化合物层之间。 该方法还包括在第二III-V化合物层上形成源特征和漏极特征，在第二III-V化合物层上形成第三III-V化合物层，在第二III -V化合物层和第三III-V化合物层的顶表面，用氟处理第二III-V化合物层的部分上的栅极电介质层，并在处理的栅极电介质层上在源特征 和排水功能。
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公开(公告)号：US20150325679A1
公开(公告)日：2015-11-12
申请号：US14790588
申请日：2015-07-02
发明人： King-Yuen Wong , Chen-Ju Yu , Jiun-Lei Jerry Yu , Po-Chih Chen , Fu-Wei Yao , Fu-Chih Yang
IPC分类号： H01L29/66 , H01L21/311 , H01L21/28 , H01L21/308 , H01L29/423 , H01L29/40 , H01L21/265 , H01L21/306
CPC分类号： H01L29/66462 , H01L21/26546 , H01L21/266 , H01L21/28264 , H01L21/30604 , H01L21/3065 , H01L21/308 , H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L21/8252 , H01L27/0605 , H01L29/2003 , H01L29/401 , H01L29/41716 , H01L29/42364 , H01L29/42372 , H01L29/66621 , H01L29/7786 , H01L29/7787
摘要： An integrated circuit device includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, a gate dielectric over the second III-V compound layer, and a gate electrode over the gate dielectric. An anode electrode and a cathode electrode are formed on opposite sides of the gate electrode. The anode electrode is electrically connected to the gate electrode. The anode electrode, the cathode electrode, and the gate electrode form portions of a rectifier.
摘要翻译： 集成电路器件包括第一III-V化合物层，第一III-V化合物层上的第二III-V化合物层，第二III-V化合物层上的栅极电介质，以及栅极电介质上的栅电极。 阳极电极和阴极电极形成在栅电极的相对侧上。 阳极电极与栅电极电连接。 阳极电极，阴极电极和栅电极形成整流器的部分。
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8.发明申请公开(公告)号：US20220359738A1
公开(公告)日：2022-11-10
申请号：US17868836
申请日：2022-07-20
发明人： Man-Ho Kwan , Fu-Wei Yao , Chun Lin Tsai , Jiun-Lei Jerry Yu , Ting-Fu Chang
IPC分类号： H01L29/778 , H01L29/10 , H01L29/20 , H01L29/66
摘要： Various embodiments of the present disclosure are directed towards an integrated chip a first undoped layer overlies a substrate. A first barrier layer overlies the first undoped layer and has a first thickness. A first doped layer overlies the first barrier layer and is disposed laterally within an n-channel device region of the substrate. A second barrier layer overlies the first barrier layer and is disposed within a p-channel device region that is laterally adjacent to the n-channel device region. The second barrier layer has a second thickness that is greater than the first thickness. A second undoped layer overlies the second barrier layer. A second doped layer overlies the second undoped layer. The second undoped layer and the second doped layer are disposed within the p-channel device region.
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公开(公告)号：US20220359681A1
公开(公告)日：2022-11-10
申请号：US17868980
申请日：2022-07-20
IPC分类号： H01L29/417 , H01L29/423 , H01L29/778 , H01L29/205 , H01L21/3213 , H01L21/02 , H01L29/20 , H01L29/66
摘要： In some embodiments, the present disclosure relates to a method of forming a transistor device. The method includes forming a source contact over a substrate, forming a drain contact over the substrate, and forming a gate contact material over the substrate. The gate contact material is patterned to define a gate structure that wraps around the source contact along a continuous and unbroken path.
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公开(公告)号：US20220359346A1
公开(公告)日：2022-11-10
申请号：US17869860
申请日：2022-07-21
IPC分类号： H01L23/48 , H01L23/522 , H01L21/768
摘要： Various embodiments of the present application are directed towards an integrated circuit (IC) chip comprising a front-end-of-line (FEOL) through semiconductor-on-substrate via (TSV), as well as a method for forming the IC chip. In some embodiments, a semiconductor layer overlies a substrate. The semiconductor layer may, for example, be or comprise a group III-V semiconductor and/or some other suitable semiconductor(s). A semiconductor device is on the semiconductor layer, and a FEOL layer overlies the semiconductor device. The FEOL TSV extends through the FEOL layer and the semiconductor layer to the substrate at a periphery of the IC chip. An intermetal dielectric (IMD) layer overlies the FEOL TSV and the FEOL layer, and an alternating stack of wires and vias is in the IMD layer.
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